cx29503 Mindspeed Technologies, cx29503 Datasheet - Page 112

• Manufacturer Part Number: cx29503
• Description: Cx29503 Broadband Access Multiplexer Data Sheet
• Manufacturer: Mindspeed Technologies

Clock Sources and Clock Configurations
4.5
Table 4-8. E3 Clock Sources and Configuration Bits in Serial E3 Interface Mode
Table 4-9. E1 Clock Sources and Configuration Bits in Serial E3 Interface Mode
4-8
Receive E3 and M13
Reference Clocks
Transmit E3 and E13
Reference Clocks
FOOTNOTE:
(1)
E1 Receive Framer Line Clock
(RCKI)
E1 Transmit Framer System
Clock (TSBCKI) and Line
Clocks (fr1_txclk_m13 and
fr1_clk_tx)
FOOTNOTE:
(1)
upl3txclkset[1:0] is located in the M13/E13 System Control registers
TXE3_CLKSEL is located in the Clock Configuration register
L3Map[1:0] is located in SONET Level 3 Mapping Control
XMTR_SEL_n[1:0] is located in Framer Control Registers 1 and 2
RCVR_SEL is located in Framer Control Register 1
FLOOP is located in the Loopback Configuration register
Description
Description
Serial E3 Interface Mode
In the serial E3 Interface mode, typically the line side of the device is connected to an
external LIU.
enabled by setting the CK_SRC[1:0] pins to 0
TXE3_CLKSEL in the Clock Configuration register in the Clock and Test (CLT)
block to 1.
Table 4-9
path is an unchannelized E3, then all E1 framers can be disabled by setting RABORT
in the Receiver Configuration register
34.368
34.368
(MHz)
(MHz)
Freq.
Freq.
2.048
2.048
lists the configuration settings depending on the timing mode. If the data
Mindspeed Technologies™
Table 4-8
System or Looped
Looped
System or Looped
System
Looped
System
Preliminary Information
(Section
Timing Mode
Timing Mode
lists the external clocking required in this mode. This mode is
(Section
(Section
8.3.1).
(Section
8.3.2.4).
(Section
8.5.7).
(Section
8.8).
(Section
M13/E13 Block
CLK_TXE1
Receive E1 Clock
Clock Source
Clock Source
8.3.1).
RLINECLK
CLK_TXE3
RLINECLK
from LIU
from LIU
8.4.1).
RXCKI
×
8.3.2.5).
2 or 0
×
3 and setting the
upl3txclkset[1:0] = 0 × 1
TXE3_CLKSEL = 0 × 1
upl3txclkset[1:0] = 0 × 0
TXE3_CLKSEL = Don't Care
upl3txclkset[1:0] = 0 × 2 or
0 × 3
TXE3_CLKSEL = Don't Care
RCVR_SEL = 0 × 0
FLOOP = 0 × 0
XMTR_SEL_n[1:0] = 0 × 00
XMTR_SEL_n[1:0] = 0 × 1X
Configuration Bits
Configuration Bits
CX29503 Data Sheet
—
29503-DSH-002-B
(1)
(1)