cx29503 Mindspeed Technologies, cx29503 Datasheet - Page 267

• Manufacturer Part Number: cx29503
• Description: Cx29503 Broadband Access Multiplexer Data Sheet
• Manufacturer: Mindspeed Technologies

CX29503 Data Sheet
0x5252—Receive AIC Byte
Value after reset:
Direction:
Value after enable:
RxAIC[7:0]
There are 8 error counters for DS3/E3 errors. All are 16-bit counters except the LCV counter, which is 24-bits.
The counters indicate 0–65,535 (LCV = 16.775215) counts of a particular error. If the interrupt for a particular
counter is not enabled, the counter will saturate at 65,535 (LCV = 16.775215). When more than 65,535
(LCV = 16.775215) counts of that error are received, the saturation indication will appear in the Counter
Interrupt Status register.
The saturation indication will be cleared when the Counter Interrupt Status register is read. The counter is
cleared when the counter is read. If the interrupt for a particular counter is enabled in the Interrupt Control
register, the counter will not saturate but will roll over and continue counting from 0. An interrupt is generated
and appears in the Counter Interrupt Status register when the counter rolls over to a count of 0. The interrupt is
cleared when the Counter Interrupt Status register is read. The counter is cleared when it is read. The counters
count according to indications set by the receiver circuit.
All counters are cleared when read by the microprocessor. The interrupt indication for a particular counter is
cleared when the Counter Interrupt Status register is read. Software should read the low byte first and then the
high byte to prevent any missed counts. All counters are designed so that errors occurring during reads by the
microprocessor will not be missed or double-counted.
The OneSec timer is a special counter that does not belong to the family of error and event counters. The
microprocessor does not read the general counter, because its only function is to count one-second intervals and
then roll over and set a status/interrupt. All counters must be in the saturating mode for this mode to function
properly.
29503-DSH-002-B
RxAIC[7]
7
RxAIC[6]
Undefined
Read only
Unaffected
Receive AIC Channel Message Byte—If the incoming format is DS3–C Bit parity, this register
contains 8 AIC (Cb11) bits from 8 consecutive frames. RxAIC[0] is the first bit received and
RxAIC[7] is the last bit received from the line. This byte is meaningless in DS3-M13/M23 and
both E3 modes and should be ignored.
6
Counters
RxAIC[5]
5
Mindspeed Technologies™
RxAIC[4]
Preliminary Information
4
RxAIC[3]
3
RxAIC[2]
2
RxAIC[1]
1
Register Description
RxAIC[0]
0
8
-
137