cx29503 Mindspeed Technologies, cx29503 Datasheet - Page 254

• Manufacturer Part Number: cx29503
• Description: Cx29503 Broadband Access Multiplexer Data Sheet
• Manufacturer: Mindspeed Technologies

Register Description
0x522D—Transmit Data Link Control Register
The Transmit Data Link (DL) Control register (CR13i) enables different modes and interrupts in the transmit
data link operation.
Default after reset:
Direction:
Modification:
TxMsgIE
TxURIE
TxNEIE
TxFCSEn
0x522E—Transmit Data Link Threshold Control Register
Default after reset:
Direction:
Modification:
TxNEThr[6:0]
8-124
Reserved
Reserved
7
7
TxNEThr[6]
Reserved
00(h)
Read/Write
Bits 1–3, dynamic; bits 0, DL-static
Transmit DL Message Transmitted Interrupt Enable—Enable interrupt due to end-of-
transmission of a full message.
Transmit DL FIFO Underrun Interrupt Enable—Enable due to data link FIFO underrun error.
Transmit DL FIFO Near-Empty Interrupt Enable—Enable interrupt due to the FIFO buffer
being near empty.
Transmit DL FCS Calculation Enable—Set to enable an FCS calculation over the transmitted
message and add it to the end of the transmitted message. When cleared, the FCS calculation
and addition are executed by the software.
00(h)
Read/Write
DL-static
Transmit DL FIFO Near-Empty Threshold—Set to the threshold value, used to indicate a near-
empty FIFO event. The range of values available for this purpose is 0–126, when 00(h) is
interpreted as 0, 01(h) is 1, etc., and 7E(h) is interpreted as 126.
6
6
NOTE:
TxNEThr[5]
Reserved
5
5
Mindspeed Technologies™
Reserved bits in control registers must be set to 0.
TxNEThr[4]
Reserved
Preliminary Information
4
4
TxNEThr[3]
TxMsgIE
3
3
TxNEThr[2]
TxURIE
2
2
TxNEThr[1]
TxNEIE
1
1
CX29503 Data Sheet
29503-DSH-002-B
TxNEThr[0]
TxFCSEn
0
0