cx29503 Mindspeed Technologies, cx29503 Datasheet - Page 74

• Manufacturer Part Number: cx29503
• Description: Cx29503 Broadband Access Multiplexer Data Sheet
• Manufacturer: Mindspeed Technologies

Functional Description
2-26
Data Link Channel Handler:
Supports the full duplex data link layer operation for the ESF Facility Data Link
(FDL) and E1 Sa4 data link
Bit-Oriented Protocol Handler
External Data Link Interface
Processing is performed by hardware; no processing by the CSP or host processor
is required
Two separate 64-byte FIFOs are used for the transmit and receive directions for
buffering the messages
Each FIFO is capable of holding multiple messages
The Receiver FIFO near full threshold can be configured in single byte
granularity
The Transmit FIFO near empty threshold can be configured in single byte
granularity
The Receive FIFO provides message receiving status, message length and
FIFO empty, near full, and full status
The Transmit FIFO provides message transmitting status, and FIFO empty,
near empty, and full status
All transmit and receive FIFO statuses have maskable interrupt capability
Supports auto-PRM transmission for every 1 second with programmable CR,
R, U1, U2, and SL control bits
Both transmit and receive FIFOs are configurable to operate in HDLC mode,
and 6- and 8-bit transparent mode
In the transparent mode, the transmit FIFO can be configured as a circular
buffer to allow data to be sent repetitively
Supports ESF bit-patterned message transmitting and receiving through the
embedded FDL channel. Includes the following:
In the E1 mode, Sa4, Sa5, Sa6, Sa7, and Sa8 can be transmitted and received
through its dedicated 8-bit buffer
Drop and insert of ESF FDL and E1 Sa4 data link to/from external HDLC
controller
Arbitration between external Message-Oriented Protocol (MOP) insertion
(from HDLC controller) and internal Bit-Oriented Protocol (BOP) insertion
(within the Framer)
– Programmable code word transmission with single, 10 repetition, 25
– Code word detection supports single, 10 repetition, and 25 repetition mode.
– The Transmitting of MOP has a higher priority
– The Framer core is responsible for inserting 27 bytes of the opening flag
– The Transmitting of BOP during data link channel idle or inactive states
repetition, or continuous modes
and 1 the byte of closing flag for each MOP message
Mindspeed Technologies™
Preliminary Information
CX29503 Data Sheet
29503-DSH-002-B