cx29503 Mindspeed Technologies, cx29503 Datasheet - Page 204

• Manufacturer Part Number: cx29503
• Description: Cx29503 Broadband Access Multiplexer Data Sheet
• Manufacturer: Mindspeed Technologies

Register Description
DL1[1: 0]
TDL1_EN
RDL1_EN
8-74
Data Link 1 Mode—Selects either HDLC-formatted Frame Check Sequence (FCS) or Non-
FCS transmit and receive data link message mode or unformatted (Pack8 or Pack6) message
mode. During HDLC modes, the transmit/receive circuits perform 0 insertion/removal after
each occurrence of 5 consecutive 1s contained in the message bits, Flag (0x7E) character
insertion/removal during idle channel conditions, and ABORT (0xFF) code insertion/detection
upon errored channel conditions. See ITU-T Recommendation Q.921 for complete details of
the HDLC link-layer protocol. FCS mode automatically generates, inserts, and checks the 16-
bit FCS without passing FCS bits through transmit and receive FIFOs.
Non-FCS mode passes all message bits that exist between the opening and closing Flag
characters through the FIFOs without generating or checking FCS bits. Non-FCS mode allows
the processor to generate and check the entire contents of each HDLC frame. Unformatted
data link modes provide transparent channel access in which every data link bit transmitted is
supplied by the processor through TDL1 and each bit received is passed to the processor
through RDL1 [addr: 0A8]. Pack8 and Pack6 unformatted mode options select the number of
bits per byte that are stored in transmit/receive FIFOs, 8 or 6 bits, respectively. The only data
processing performed during unformatted mode is the alignment of transmitted and received
data bits with respect to the transmit/receive multiframe.
Transmit Data Link 1 Enable—When enabled, the transmitter begins to empty and format the
contents of the transmit data link FIFO for output during the selected time slot bits according
to the selected DL1[1:0] mode. Also enables generation of transmitter data link interrupt
events.
Receive Data Link 1 Enable—When enabled, the receiver begins to format data from the
selected time slot bits and to fill the receive data link FIFO according to the selected DL1[1:0]
mode. Also enables generation of receiver data link interrupt events.
00 = FCS
01 = No FCS
10 = Pack8
11 = Pack6
0 = disabled
1 = enable transmit data link
0 = disabled
1 = enable receive data link
Mindspeed Technologies™
Preliminary Information
CX29503 Data Sheet
29503-DSH-002-B