cx29503 Mindspeed Technologies, cx29503 Datasheet - Page 293

• Manufacturer Part Number: cx29503
• Description: Cx29503 Broadband Access Multiplexer Data Sheet
• Manufacturer: Mindspeed Technologies

CX29503 Data Sheet
8.5
The SONET/SDH Mapper block implements an 11-bit, byte-addressable address space. The memory map is
divided into 32 functional groupings, 4 STS-1/TUG-3 and global groups, and 28 VT/VC groups. This section
defines the STS-1/TUG-3 and global groupings.
Table 8-53. SONET/SDH Block Memory Map
8.5.1
The SONET/SDH Mapper block is brought to a known, nonfunctional initial state through hardware reset.
8.5.2
The SONET/SDH Mapper module has numerous modes. Each mode needs to be configured via software before
the mode becomes functional.
8.5.2.1
29503-DSH-002-B
0x6000–0x60FF
0x6100–0x61FF
0x6200–0x62FF
0x6300–0x63FF
Group Offset
SONET/SDH Block
Initialization
Software Configuration/Setup
DS3 and E3 Modes
1.
2.
3.
4.
5.
6.
7.
For DS3 mode, set the L3MAP[1:0] bits in the Level 3 Mapping Control register
(0x6380) to 0x02 for DS3 mapping. Set the TUG3 bit to 0 for STS-1/AU-3
mapping, or 1 for TUG-3 mapping.
For E3 mode, set the L3MAP[1:0] bits in the Level 3 Mapping Control register
(0x6380) to 0x03 for E3 mapping. Set the TUG3 bit to 0 for STS-1/AU-3
mapping, or 1 for TUG-3 mapping.
Set the TXL3MAPMIN register (0x620E) to 0x30 to set the minimum level of the
mapper FIFO to 48 bytes.
Set the RXL3DEMMIN register (0x628E) to 0x80 to set the minimum level of
the demapper FIFO to 128 bytes.
Write a “0x00 → 0x01 → 0x00” sequence to the TXL3MAPRST register
(0x620F) to reset the mapper FIFO.
Write a “0x00 → 0x01 → 0x00” sequence to the RXL3DEMRST register
(0x628F) to reset the demapper FIFO and the smoother
At this point, the module is configured in DS3 or E3 mode. Clear all status
registers and interrupts to remove any errors generated during the configuration
process.
General Control and Status
STS-1 Framer Section and Line Control/Status
(Section
Path Control and Status
Mapping Control and Status
Mindspeed Technologies™
8.5.5)
Preliminary Information
Section 8.6
Register Functional Group
(Section
(Section
(Section
defines the memory map for the 28 VT/VC groups.
8.5.6)
8.5.4)
8.5.7)
page -167
page -181
page -182
page -203
Register Description
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