cx29503 Mindspeed Technologies, cx29503 Datasheet - Page 205

• Manufacturer Part Number: cx29503
• Description: Cx29503 Broadband Access Multiplexer Data Sheet
• Manufacturer: Mindspeed Technologies

CX29503 Data Sheet
0xA7—RDL 1 FIFO Fill Control (RDL1_FFC)
MSG_FILL[1:0]
FFC[5:0]
29503-DSH-002-B
MSG_FILL[1]
7
MSG_FILL[0]
Unformatted Message Fill Limit—Applicable only for Pack8 and Pack6 modes, the message
fill limit selects the number of receive FIFO locations [RDL1; addr: 0A8] to be filled before
the receive data link generates an RFULL interrupt [ISR2; addr: 009] and a corresponding
RDL1 partial message status word entry. The Fill limit determines how many bytes constitute
an unformatted message. Fill limits give the processor an alternative to using RNEAR
interrupts to signal the end of a received unformatted message.
For example, SLC applications monitor Fs bits during even frames for a total of 36 bits
monitored out of 72 frames. Using Pack6 mode, that group of 36 Fs bits from each SLC
multiframe can be chosen to constitute one unformatted message by selecting a message fill
limit which equals 6 bytes (of 6 bits/byte). In the SLC example, an RFULL interrupt would
then be generated every 9 ms on each SLC multiframe boundary. Fill limits provided for T1
cases are multiples of 6 bytes (i.e., 6, 12, or 18 FIFO locations) to hold 1 or more multiframes’
worth of monitored data. In E1 mode, fill limits are multiples of 8 bytes to correspond with the
16-frame multiframe lengths (i.e., monitoring CRC4 in MFAS framing mode).
Near-Full FIFO Threshold—Selects FIFO depth of near-full interrupt [RNEAR1; addr: 009]
and near-full level status [RNEAR1; addr: 0A9]. The RNEAR1 interrupt and RNEAR1
indicator are both activated when the number of empty FIFO locations equals the selected
threshold. The threshold controls how many data and/or status bytes (64 minus threshold
value) that the processor must read from RDL1 after RNEAR1 interrupt. This is done to clear
the RNEAR1 indicator as well as to determine how much time remains (in bytes) for the
processor to read RDL1 before the receive FIFO is full. If a receive message is in progress
when the near-full threshold is reached, the receiver issues a message interrupt
[RMSG; addr: 009] and places a partial message in the receive FIFO.
6
Table 8-34. Message Fill Limits
NOTE:
T1/E1N
FFC[5]
X
0
0
0
1
1
1
5
Mindspeed Technologies™
The number of bits per unformatted message must divide evenly by the number of
bits monitored per multiframe.
FFC[4]
Preliminary Information
4
MSG_FILL[1:0]
00
01
10
11
01
10
11
FFC[3]
3
FFC[2]
2
Message Fill Limit
FFC[1]
Disabled
16 bytes
24 bytes
12 bytes
18 bytes
6 bytes
8 bytes
1
Register Description
FFC[0]
0
8
-
75