cx29503 Mindspeed Technologies, cx29503 Datasheet - Page 162

• Manufacturer Part Number: cx29503
• Description: Cx29503 Broadband Access Multiplexer Data Sheet
• Manufacturer: Mindspeed Technologies

Register Description
0x0B—Pattern Interrupt Status (ISR0)
All events in ISR0 are from rising edge sources. Each event is latched active-high and held until the processor
read clears ISR0. Each event triggers an interrupt if the corresponding IER0 bit is enabled [addr: 013].
Unused bits are reserved and should be written to 0.
PSYNC
8.3.2.3
Writing a one to an IER bit allows that specific interrupt source to activate its respective ISR and IRR bits, and
report the interrupt to the Global Control and Status block. If cleared, each IER bit allows that source to activate
its respective ISR bit, but prevents activation of the IRR bit and reporting the interrupt to the Global Control and
Status block.
0x0C—Alarm 1 Interrupt Enable Register (IER7)
Reserved bits should be written to 0.
RMYEL
RYEL
RAIS
RLOS
RLOF
8-32
RMYEL
—
7
7
Receive Pseudo-Random Bit Sequence (PRBS) Test Pattern Synchronization—Forced to
inactive (low) status when the processor requests RESEED [addr: 041] of the PRBS sync
detector and remains low while the detector searches for test pattern synchronization. PRBS bit
errors [BERR; addr: 058, 059] are not counted while PSYNC is low. PSYNC remains low for a
minimum of 128 bits following RESEED and for as long as the received BER exceeds 10
PSYNC is latched active (high) and the PRBS synchronization detector stops searching when no
bit errors are found for a period of 96 bits. The synchronization detector remains disabled until
the processor requests another RESEED. Therefore, any range of BER can be measured after the
initial pattern synchronization. The processor must determine criteria for loss of pattern sync
based on its accumulation of bit errors over the desired time interval.
Enable RMYEL Interrupt
Enable RYEL Interrupt
Enable RAIS Interrupt
Enable RLOS Interrupt
Enable RLOF Interrupt
RYEL
—
6
6
0 = no synchronization
1 = PRBS test pattern synchronization
Interrupt Enable Registers (IER)
RESERVED
—
5
5
Mindspeed Technologies™
PSYNC
Preliminary Information
RAIS
4
4
RESERVED
RESERVED
3
3
RESERVED
RLOS
2
2
RESERVED
RLOF
1
1
CX29503 Data Sheet
29503-DSH-002-B
RESERVED
RESERVED
0
0
-2
.