cx29503 Mindspeed Technologies, cx29503 Datasheet - Page 385

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cx29503

Manufacturer Part Number
cx29503
Description
Cx29503 Broadband Access Multiplexer Data Sheet
Manufacturer
Mindspeed Technologies
Datasheet
Revision History
29503-DSH-002-B
Revision
A
A
B
Appendix C: Revision History
Advance
Advance
Advance
Level
Mindspeed Technologies™
November 2002
January 2001
Preliminary Information
August 2002
Date
Initial Release. Document No.100702A
Document No. 500238A
• Removed support for Motorola 68K microprocessor.
• Added register 0x0A to DS1/E1 framer block.
• Changed timing on TSB_TDAT
• Moved location of InsAIS-P in Transmit Path
• Added M13/E13 channel numbers and cross-
• Updated Idd and Iddio consumption estimates.
• Updated timing information for:
• Removed B3SZ/HDB3 encode/decode block. B3SZ/
• Deleted material related to TSB bypass.
• Added section about Unframed DS1/E1 Mode
• Added TSBUS TSB_TSYNCI interface timing
• Added TSBUS TSB_RSYNCI interface timing
• Added unframed link control registers
• Deleted material related to BSLIP.
• Deleted Error Inertion 1 and 2 control registers
• Updated absolute maximum ratings over operating
• Other minor revisions
Restored INS_YEL bit (bit #4) to register 0x72—Trans-
mit Frame Format (TFRM). Removed references to
PSLIP buffers.Removed support for MPC860 micropro-
cessor interface.
Overhead Control register (0x6200).
references to DS1/E1 framer numbers.
1. MPC860
2. E-Bus
3. Serial DS3/E3
HDB3 encoding/decoding is performed by DS3/E3
framer block.
diagram
diagram
free-air temperature ratings table
Description
(Figure
2-19).
C
-
1

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