cx29503 Mindspeed Technologies, cx29503 Datasheet - Page 261

• Manufacturer Part Number: cx29503
• Description: Cx29503 Broadband Access Multiplexer Data Sheet
• Manufacturer: Mindspeed Technologies

CX29503 Data Sheet
0x5244—Alarm End Interrupt Status Register
The Alarm End Interrupt Status register provides indications of the ending of continuous events. The event bit is
cleared when the register is read. In addition, the event bit is cleared upon setting the channel’s enable bit for
that event to prevent an immediate interrupt due to an old event.
Value after reset:
Direction:
Value after enable:
LOSEnd
IdleEnd
YelEnd
AISEnd
OOFEnd
0x5246—E3-G.832 MA Fields Status Register
The CX29503 does not support E3-G.832 mode. This register is reserved.
0x5247—E3-G.832 SSM Field Status Register
The CX29503 does not support E3-G.832 mode. This register is reserved.
29503-DSH-002-B
Reserved
7
Reserved
00(h)
Read only
00(h)
LOS Event End—Set when the received signal, prior to B3ZS/HDB3 decoding, satisfies the
criteria of the correct signal after being in an LOS state. This bit is cleared when this register is
read.
Idle Event End—Set when the receiver detects an end of an Idle event in DS3 mode. This bit is
cleared when this register is read. This bit will be low in E3 modes because there is no defined
E3 idle signal.
Yellow Alarm End—Set when the receiver detects an end of an RAI/RDI alarm. This bit is
cleared when this register is read.
AIS Alarm End—Set when the receiver detects an end of an AIS alarm. This bit is cleared
when this register is read.
OOF Event End—Set when the channel goes into the in-frame state again after being in an
OOF state. This bit is cleared when this register is read.
6
Reserved
5
Mindspeed Technologies™
LOSEnd
Preliminary Information
4
IdleEnd
3
YelEnd
2
AISEnd
1
Register Description
OOFEnd
0
8
-
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