cx29503 Mindspeed Technologies, cx29503 Datasheet - Page 296

• Manufacturer Part Number: cx29503
• Description: Cx29503 Broadband Access Multiplexer Data Sheet
• Manufacturer: Mindspeed Technologies

Register Description
Figure 8-7. SONET/SDH Interrupt Structure—Receive Path
8-166
VT#n Receive VT Start of Status IE 1 [addr: 0xB3]
VT#n Receive VT Start of Status IE 2 [addr: 0xB4]
VT#n Receive VT End of Status IE 1 [addr: 0xB5]
VT#n Receive VT End of Status IE 2 [addr: 0xB6]
VT#n Receive VT Start of Status 1 [addr: 0xBB]
VT#n Receive VT Start of Status 2 [addr: 0xBC]
VT#n Receive VT End of Status 1 [addr: 0xBD]
VT#n Receive VT Event Status IE [addr: 0xB7]
VT#n Receive VT End of Status 2 [addr: 0xBE]
VT#n Receive VT Event Status [addr: 0xBF]
Transmit Channel Interrupt
Receive Channel Interrupt
Enable [addr: 6088–608B]
Status [addr: 608C–608F]
The receive interrupt structure is shown in
clear-on-read type. The Level 2 interrupt source and Level 3 interrupt status bits are
not clear-on-read type and are cleared when the related Level 1 status bits are cleared.
Receive Tributary Start of Status IE [addr: 62F3]
Receive Tributary End of Status IE [addr: 62F5]
Receive Tributary Event Status IE [addr: 62F7]
Receive Path Start of Status IE 1 [addr: 62B3]
Receive Path Start of Status IE 2 [addr: 62B4]
Receive Tributary Start of Status [addr: 62FB]
Receive Path End of Status IE 1 [addr: 62B5]
Receive Path End of Status IE 2 [addr: 62B6]
Receive Tributary End of Status [addr: 62FD]
Receive Tributary Event Status [addr: 62FF]
Receive Path Start of Status 2 [addr: 62BC]
Receive Path Start of Status 1 [addr: 62BB]
Receive Path End of Status 1 [addr: 62BD]
Receive Path End of Status 2 [addr: 62BE]
Receive Path Event Status IE [addr: 62B7]
Receive Path Event Status [addr: 62BF]
VT#n Receive VT
Interrupt Source
[addr: 0xB0]
Mindspeed Technologies™
Preliminary Information
Interrupt Statuses
Interrupt Enables
Enable Bits
Status Bits
VT/VC 1–28
VT/VC 1–28
OR
Status Bits
1–28
. . .
. . .
. . .
OR
Receive STS/SDH Mapper Block Interrupt
Enable Bits
Status Bits
(see Figure 2-20)
Interrupt Enable
Interrupt Status
OR
Figure
STS Path
STS Path
Status Bits
OR
OR
8-7. The Level 1 status bits are the
Path Interrupt
Receive STS
[addr: 62B0]
Source
Enable Bits
Interrupt Enable
Interrupt Status
Status Bits
General
General
OR
Receive SI-Bus
IE [addr: 6080]
Receive SI-Bus
Status [addr: 6081]
CX29503 Data Sheet
29503-DSH-002-B
100702_044