cx29503 Mindspeed Technologies, cx29503 Datasheet - Page 155

• Manufacturer Part Number: cx29503
• Description: Cx29503 Broadband Access Multiplexer Data Sheet
• Manufacturer: Mindspeed Technologies

CX29503 Data Sheet
0x03—Interrupt Request Register (IRR)
An IRR bit is latched active (high) whenever an enabled interrupt source reports an interrupt event in the
corresponding Interrupt Status Register [ISR7–ISR0; addr: 004–00B]. The IRR is latched until the
corresponding ISR register is read by the processor. Reading ISR clears the respective IRR bit, independent of
clearing ISR bits. Therefore, persistently active ISR bits will not affect INTR* deactivation.
All IRR bits are logically ORed to activate a corresponding bit in the DS1/E1 Framer Interrupt Request registers
[FR_IRR1–FR_IRR4 in the Global Control and Status block] so the processor must read IRR = 00 before
exiting its interrupt service routine to confirm that the DS1/E1 Framer Interrupt Request Register bit has been
deasserted.
The DS1/E1 Framer Interrupt structure is shown in
interrupt request.
Figure 8-1. DS1/E1 Framer Interrupt Structure
29503-DSH-002-B
Action
Taken
Level
Level
Level
Top Level—Contains the interrupt request status from 28 DS1/E1 framers. Four register reads are required
in order to identify which framer is requesting service.
2
required in order to determine which functional block is requesting service.
3
before servicing the request.
nd
rd
Top
2nd
3rd
Level—Contains the interrupt source within the particular functional block. One register read is required
Level—Contains the interrupt request from 7 functional blocks in each framer core. One register read is
INTERRUPT
INTERRUPT
ALARM 1
RMYEL
Framers 1–8
RLOS
RYEL
RLOF
IRR
RAIS
FR_IRR 1
INTERRUPT
ALARM 2
LOOPDN
LOOPUP
ONESEC
Mindspeed Technologies™
A Common Interrupt Request for All 28 Framers
Framers 9–16
INTERRUPT
FR_IRR 2
MERR
ERROR
CERR
FERR
Preliminary Information
Figure
INTERRUPT
COUNT
FRED
COFA
BERR
FEBE
FERR
CRC
SEF
8-1. It requires searching 3 levels to respond to an
Framers 17–24
FR_IRR 3
INTERRUPT
RMFRAME
TFRAME
TIMER
RMF
TMF
INTERRUPT
TDLERR
TEMPTY
RNEAR
TNEAR
RFULL
RMSG
TMSG
TBOP
DL1
Framers 25–28
FR_IRR 4
Register Description
INTERRUPT
PSYNC
PATT
100702_040
8
-
25