cx29503 Mindspeed Technologies, cx29503 Datasheet - Page 209

• Manufacturer Part Number: cx29503
• Description: Cx29503 Broadband Access Multiplexer Data Sheet
• Manufacturer: Mindspeed Technologies

CX29503 Data Sheet
0xAA—Performance Report Message (PRM)
Reserved bits should be written to 0.
AUTO_PRM
29503-DSH-002-B
AUTO_PRM
7
PRM_CR
Automatic PRM Insertion—AUTO_PRM instructs the data link transmitter to format and send
a PRM on the selected transmit channel after each occurrence of the OneSec interrupt. To
meet PRM requirements specified in ANSI T1.403-1995, FCS mode [DL1_CTL; addr: 0A6]
and One-Second error count latching [LATCH_CNT; addr: 046] must both be enabled. In
addition, the data link channel must be selected to output on Facility Data Link (FDL) framing
bits [DL1_TS = 0x40; addr: 0A4]. Octets 1–14 of the transmit PRM message contents are
automatically encoded (see
CRC, FPS, SEF, and FRED errors [addr: 050–05A]. The remaining PRM message contents
typically remain fixed and are supplied by the processor from other bits that follow in the PRM
register.
6
0 = no automatic PRM
1 = send PRM automatically every OneSec
NOTE:
NOTE:
PRM_R
5
Mindspeed Technologies™
BOP priority code word transmissions are interrupted by AUTO_PRM if TDL1 is
granted output priority [TBOP_MODE = 11; addr: 0A0].
The AUTO_PRM messages take up no space in the transmit data link FIFO, but are
inserted on the transmit channel only after the FIFO is empty. Therefore, if the
processor needs to transmit another type of FDL message between PRM messages,
the processor must write that message after AUTO_PRM has begun sending (i.e.,
after OneSec interrupt).
PRM_U1
Table
Preliminary Information
4
8-36). The encodings are based on the number of received
PRM_U2
3
PRM_SL
2
RESERVED
1
Register Description
SEND_PRM
0
8
-
79