cx29503 Mindspeed Technologies, cx29503 Datasheet - Page 363

• Manufacturer Part Number: cx29503
• Description: Cx29503 Broadband Access Multiplexer Data Sheet
• Manufacturer: Mindspeed Technologies

CX29503 Data Sheet
8.8
This section describes all registers within each Clock and Test (CLT) block. The register maps for each block
are given in
Table 8-62. CLT Register Map
0xA000—Clock Configuration
Reset State
ONE_HZ_OEN
TXE3_CLKSEL
0xA001—Test Bus Configuration (Used for Diagnostics)
Reset State
TSTBUS_SEL
29503-DSH-002-B
Reserved
Reserved
7
Offset (Hex)
7
0xA000
0xA001
Table
Reserved
Reserved
0x1
When 0, the CLK_1HZ pin is configured as an output (resets to an input state).
Selects between CLK_TXDS3 and CLK_TXE3. A value of 1 selects CLK_TXE3. A value
of 0 selects CLK_TXDS3. This bit is used in conjunction with the upl3txclksel[1:0] in the
M13/E13 System Control register (see
clocks. It is also used in conjunction with the CLK_SRC[1:0] pins to select the clocks for the
CSP.
0x0
Selects various signals to output on TST_BUS[17:0].
8-38.
6
Clock and Test
6
Type
R/W
R/W
Reserved
Reserved
5
5
Clear on Read
Mindspeed Technologies™
Reserved
No
No
TSTBUS_SEL[
4
Preliminary Information
4]
4
Reserved
Section
TSTBUS_SEL[
3
Register Description
Test Bus Configuration
3]
3
Clock Configuration
8.4.1) for the Transmit DS3/E3 and M3/E13
Reserved
TSTBUS_SEL[
2
2]
2
TXE3_CLKSEL
TSTBUS_SEL[
1
1]
1
Reset (Hex)
Value after
Register Description
0x01
0x00
ONE_HZ_OEN
TSTBUS_SEL[
0
0]
0
8
-
233