ADUC7025BCPZ32-RL7 AD [Analog Devices], ADUC7025BCPZ32-RL7 Datasheet
ADUC7025BCPZ32-RL7
Related parts for ADUC7025BCPZ32-RL7
ADUC7025BCPZ32-RL7 Summary of contents
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FEATURES Analog I/O Multichannel, 12-bit, 1 MSPS ADC ADC channels Fully differential and single-ended modes analog input range REF 12-bit voltage output DACs DAC outputs available On-chip voltage reference ...
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ADuC7019/20/21/22/24/25/26/27 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 3 General Description ......................................................................... 4 Detailed Block Diagram .............................................................. 5 Specifications..................................................................................... 6 Timing Specifications .................................................................. 9 Absolute Maximum Ratings.......................................................... 16 ESD Caution................................................................................ 16 ...
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Hardware Design Considerations .................................................83 Power Supplies.............................................................................83 Grounding and Board Layout Recommendations .................84 Clock Oscillator...........................................................................84 Power-on Reset Operation.........................................................85 Typical System Configuration ...................................................85 Development Tools .........................................................................86 REVISION HISTORY 1/06—Rev Rev. A Changes to Table 1 ............................................................................6 Added the Flash/EE Memory ...
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ADuC7019/20/21/22/24/25/26/27 GENERAL DESCRIPTION The ADuC7019/7020/7021/7022/7024/7025/7026/7027 are fully integrated, 1 MSPS, 12-bit data acquisition systems incorporat- ing high performance multichannel ADCs, 16-bit/32-bit MCUs and Flash/EE memory on a single chip. The ADC consists single-ended inputs. An additional ...
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ADC0 77 ADC1 78 12-BIT SAR ADC2/CMP0 79 ADC 1MSPS ADC3/CMP1 80 ADC4 1 ADC5 2 ADC6 3 MUX ADC7 4 ADC8 5 ADC9 6 ADC10 7 ADC11 76 TEMP SENSOR ADCNEG 9 MUX ...
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ADuC7019/20/21/22/24/25/26/27 SPECIFICATIONS AVDD = IOV = 2 3 2.5 V internal reference REF Table 1. Parameter ADC CHANNEL SPECIFICATIONS ADC Power-Up Time Accuracy Resolution Integral Nonlinearity 3, 4 Differential Nonlinearity ...
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Parameter ANALOG OUTPUTS Output Voltage Range_0 Output Voltage Range_1 Output Voltage Range_2 Output Impedance DAC AC CHARACTERISTICS Voltage Output Settling Time Digital to Analog Glitch Energy COMPARATOR Input Offset Voltage Input Bias Current Input Voltage Range Input Capacitance 4, 6 ...
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ADuC7019/20/21/22/24/25/26/27 Parameter INTERNAL OSCILLATOR MCU CLOCK RATE From 32 kHz Internal Oscillator From 32 kHz External Crystal Using an External Clock START-UP TIME At Power-On From Pause/Nap Mode From Sleep Mode From Stop Mode PROGRAMMABLE LOGIC ARRAY (PLA) Pin Propagation ...
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TIMING SPECIFICATIONS Table 2. External Memory Write Cycle Parameter Min CLK T 0 MS_AFTER_CLKH T 4 ADDR_AFTER_CLKH T AE_H_AFTER_MS HOLD_ADDR_AFTER_AE_L T HOLD_ADDR_BEFORE_WR_L T WR_L_AFTER_AE_L T 8 DATA_AFTER_WR_L WR_H_AFTER_CLKH T HOLD_DATA_AFTER_WR_H T BEN_AFTER_AE_L T ...
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ADuC7019/20/21/22/24/25/26/27 Table 3. External Memory Read Cycle Parameter Min CLK T 4 MS_AFTER_CLKH T 4 ADDR_AFTER_ CLKH T AE_H_AFTER_MS HOLD_ADDR_AFTER_AE_L T RD_L_AFTER_AE_L T 8 DATA_AFTER_RD_L RD_H_AFTER_CLKH T HOLD_DATA_AFTER_RD_H T RELEASE_MS_AFTER_RD_H CLK ECLK T ...
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Table Timing in Fast Mode (400 kHz) Parameter Description t SCLOCK low pulse width L t SCLOCK high pulse width H t Start condition hold time SHD t Data setup time DSU t Data hold time ...
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ADuC7019/20/21/22/24/25/26/27 Table 5. SPI Master Mode Timing (PHASE Mode = 1) Parameter Description t SCLOCK low pulse width SL t SCLOCK high pulse width SH t Data output valid after SCLOCK edge DAV t Data input setup time before SCLOCK ...
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Table 6. SPI Master Mode Timing (PHASE Mode = 0) Parameter Description t SCLOCK low pulse width SL t SCLOCK high pulse width SH t Data output valid after SCLOCK edge DAV t Data output setup before SCLOCK edge DOSU ...
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ADuC7019/20/21/22/24/25/26/27 Table 7. SPI Slave Mode Timing (PHASE Mode = 1) Parameter Description SCLOCK edge CS t SCLOCK low pulse width SL t SCLOCK high pulse width SH t Data output valid after SCLOCK edge DAV ...
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Table 8. SPI Slave Mode Timing (PHASE Mode = 0) Parameter Description SCLOCK edge CS t SCLOCK low pulse width SL t SCLOCK high pulse width SH t Data output valid after SCLOCK edge DAV t ...
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ADuC7019/20/21/22/24/25/26/27 ABSOLUTE MAXIMUM RATINGS AGND = REFGND = DACGND = GND T = 25°C, unless otherwise noted. A Table 9. Parameter AV to IOV DD DD AGND to DGND IOV to IOGND AGND DD DD Digital Input Voltage ...
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PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS ADuC7019/ADuC7020/ADuC7021/ADuC7022 ADC3/CMP1 1 PIN 1 ADC4 2 INDICATOR GND 3 REF DAC0/ADC12 4 ADuC7019/ DAC1/ADC13 5 ADuC7020 DAC2/ADC14 6 TOP VIEW DAC3/ADC15 7 (Not to Scale) TMS 8 TDI 9 BM/P0.0/CMP /PLAI[7] 10 OUT Figure ...
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ADuC7019/20/21/22/24/25/26/27 Table 10. Pin Function Descriptions (ADuC7019/ADuC7020/ADuC7021/ADuC7022) Pin No. 7019/7020 7021 7022 Mnemonic ADC0 ADC1 ADC2/CMP0 ADC3/CMP1 ADC4 ‒ ADC5 ‒ ...
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Pin No. 7019/7020 7021 7022 Mnemonic XCLKI P1.7/SPM7/PLAO[ P1.6/SPM6/PLAI[ P1.5/SPM5/PLAI[5]/IRQ3 P1.4/SPM4/PLAI[4]/IRQ2 P1.3/SPM3/PLAI[ P1.2/SPM2/PLAI[ P1.1/SPM1/PLAI[ ...
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ADuC7019/20/21/22/24/25/26/27 ADuC7024/ADuC7025 P4.6/PLAO[14] P4.7/PLAO[15] BM/P0.0/CMP P0.6/T1/MRST/PLAO[3] DAC0/ADC12 DAC1/ADC13 P4.6/PLAO[14] P4.7/PLAO[15] BM/P0.0/CMP P0.6/T1/MRST/PLAO[3] ADC4 1 PIN 1 ADC5 2 ADC6 3 INDICATOR ADC7 4 ADC8 5 ADuC7024/ ADC9 6 GND 7 ADuC7025 REF ADCNEG 8 TOP VIEW DAC0/ADC12 9 (Not to ...
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Table 11. Pin Function Descriptions (ADuC7024/ADuC7025 64-Lead CSP and ADuC7024/ADuC7025 64-Lead LQFP) Pin No. Mnemonic 1 ADC4 2 ADC5 3 ADC6 4 ADC7 5 ADC8 6 ADC9 7 GND REF 8 ADCNEG 9 DAC0/ADC12 10 DAC1/ADC13 11 TMS 12 TDI ...
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ADuC7019/20/21/22/24/25/26/27 Pin No. Mnemonic 36 XCLKI 37 P3.6/PWM /PLAI[14] TRIP 38 P3.7/PWM /PLAI[15] SYNC 39 P1.7/SPM7/PLAO[0] 40 P1.6/SPM6/PLAI[6] 41 IOGND 42 IOV DD 43 P4.0/PLAO[8] 44 P4.1/PLAO[9] 45 P1.5/SPM5/PLAI[5]/IRQ3 46 P1.4/SPM4/PLAI[4]/IRQ2 47 P1.3/SPM3/PLAI[3] 48 P1.2/SPM2/PLAI[2] 49 P1.1/SPM1/PLAI[1] 50 P1.0/T1/SPM0/PLAI[0] 51 ...
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ADuC7026/ADuC7027 ADC4 ADC5 ADC6 ADC7 ADC8 ADC9 ADC10 GND REF ADCNEG DAC0/ADC12 DAC1/ADC13 DAC2/ADC14 DAC3/ADC15 TMS TDI P0.1/PWM2 /BLE H P2.3/AE P4.6/AD14/PLAO[14] P4.7/AD15/PLAO[15] BM/P0.0/CMP /PLAI[7]/MS2 OUT Table 12. Pin Function Descriptions (ADuC7026/ADuC7027) Pin No. Mnemonic 1 ADC4 2 ADC5 3 ...
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ADuC7019/20/21/22/24/25/26/27 Pin No. Mnemonic 14 TMS 15 TDI 16 P0.1/PWM2 /BLE H 17 P2.3/AE 18 P4.6/AD14/PLAO[14] 19 P4.7/AD15/PLAO[15] 20 BM/P0.0/CMP /PLAI[7]/MS2 OUT 21 P0.6/T1/MRST/PLAO[3]/AE 22 TCK 23 TDO 24 P0.2/ PWM2 /BHE L 25 IOGND 26 IOV ...
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Pin No. Mnemonic 43 P0.7/ECLK/XCLK/SPM8/ PLAO[4] 44 XCLKO 45 XCLKI 46 P3.6/AD6/PWM /PLAI[14] TRIP 47 P3.7/AD7/PWM /PLAI[15] SYNC 48 P2.7/PWM1 /MS3 L 49 P2.1/WS/PWM0 /PLAO[ P2.2/RS/PWM0 /PLAO[ P1.7/SPM7/PLAO[0] 52 P1.6/SPM6/PLAI[6] 53 IOGND 54 IOV DD 55 ...
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ADuC7019/20/21/22/24/25/26/27 Pin No. Mnemonic 75 DACV DD 76 ADC11 77 ADC0 78 ADC1 79 ADC2/CMP0 80 ADC3/CMP1 Description 3.3 V Power Supply for the DACs. Typically connected to AV Single-Ended or Differential Analog Input 11. Single-Ended or Differential Analog Input ...
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TYPICAL PERFORMANCE CHARACTERISTICS 1 774kSPS S 0.8 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 0 1000 2000 ADC CODES Figure 16. Typical INL Error 1 1MSPS S 0.8 0.6 0.4 0.2 0 ...
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ADuC7019/20/21/22/24/25/26/27 9000 8000 7000 6000 5000 4000 3000 2000 1000 0 1161 1162 BIN Figure 22. Code Histogram Plot 774 kSPS –20 –40 –60 –80 –100 –120 –140 –160 0 100 FREQUENCY (kHz) Figure 23. Dynamic ...
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TEMPERATURE (°C) Figure 28. Current Consumption vs. Temperature @ 7.85 7.80 7.75 7.70 7.65 7.60 7.55 7.50 7.45 7.40 – ...
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ADuC7019/20/21/22/24/25/26/27 TERMINOLOGY ADC SPECIFICATIONS Integral Nonlinearity The maximum deviation of any code from a straight line passing through the endpoints of the ADC transfer function. The endpoints of the transfer function are zero scale, a point ½ LSB below the ...
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OVERVIEW OF THE ARM7TDMI CORE The ARM7® core is a 32-bit reduced instruction set computer (RISC). It uses a single 32-bit bus for instruction and data. The length of the data can be 8 bits, 16 bits bits. ...
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ADuC7019/20/21/22/24/25/26/ R8_FIQ R8 R9_FIQ R9 R10_FIQ R10 R11_FIQ R11 R12_FIQ R13_ABT R12 R13_SVC R13_FIQ R14_ABT R13 R14_SVC R14_FIQ R14 R15 (PC) SPSR_ABT SPSR_SVC CPSR SPSR_FIQ FIQ SVC ABORT USER MODE MODE MODE ...
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MEMORY ORGANIZATION The ADuC7019/7020/7021/7022/7024/7025/7026/7027 incorporate two separate blocks of memory SRAM and on-chip Flash/EE memory. Sixty-two kilobytes of on- chip Flash/EE memory is available to the user, and the remaining 2 kB are reserved ...
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ADuC7019/20/21/22/24/25/26/27 0xFFFFFFFF 0xFFFFFC3C PWM 0xFFFFFC00 0xFFFFF820 FLASH CONTROL INTERFACE 0xFFFFF800 0xFFFFF46C GPIO 0xFFFFF400 0xFFFF0B54 PLA 0xFFFF0B00 0xFFFF0A14 SPI 0xFFFF0A00 0xFFFF0948 0xFFFF0900 0xFFFF0848 0xFFFF0800 0xFFFF0730 UART 0xFFFF0700 0xFFFF0620 DAC 0xFFFF0600 0xFFFF0538 ADC 0xFFFF0500 0xFFFF0490 BAND ...
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Access Address Name Byte Type ADC address base = 0xFFFF0500 0x0500 ADCCON 2 R/W 0x0504 ADCCP 1 R/W 0x0508 ADCCN 1 R/W 0x050C ADCSTA 1 R 0x0510 ADCDAT 4 R 0x0514 ADCRST 1 R/W 0x0530 ADCGN 2 R/W 0x0534 ADCOF ...
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ADuC7019/20/21/22/24/25/26/27 Access Address Name Byte Type PLA base address = 0xFFFF0B00 0x0B00 PLAELM0 2 R/W 0x0B04 PLAELM1 2 R/W 0x0B08 PLAELM2 2 R/W 0x0B0C PLAELM3 2 R/W 0x0B10 PLAELM4 2 R/W 0x0B14 PLAELM5 2 R/W 0x0B18 PLAELM6 2 R/W 0x0B1C ...
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ADC CIRCUIT OVERVIEW The analog-to-digital converter (ADC) incorporates a fast, multichannel, 12-bit ADC. It can operate from 2 3.6 V supplies and is capable of providing a throughput MSPS when the clock source is ...
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ADuC7019/20/21/22/24/25/26/27 SIGN BIT 0 1111 1111 1110 2 × V REF 1LSB = 0 1111 1111 1100 4096 0 1111 1111 1010 0 0000 0000 0010 0 0000 0000 0000 1 1111 1111 1110 1 0000 0000 0100 1 0000 ...
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Table 14. ADCCON MMR Bit Designations Bit Value Description 15:13 Reserved. 12:10 ADC clock speed. 000 fADC/1. This divider is provided to obtain 1 MSPS ADC with an external clock <41.78 MHz. 001 fADC/2 (default value). 010 fADC/4. 011 fADC/8. ...
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ADuC7019/20/21/22/24/25/26/27 ADCCN Register Name Address Default Value ADCCN 0xFFFF0508 0x01 ADCCN is an ADC negative channel selection register. This MMR is described in Table 16. Table 16. ADCCN MMR Bit Designation Bit Value Description 7:5 Reserved 4:0 Negative channel selection ...
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CHANNEL+ AIN0 A SW1 MUX SW3 C SW2 S CHANNEL– A AIN11 B V REF Figure 43. ADC Conversion Phase Pseudo Differential Mode In pseudo differential mode, Channel− is linked to the V of the ADuC7019/7020/7021/7022/7024/7025/7026/7027. SW2 ...
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ADuC7019/20/21/22/24/25/26/27 DRIVING THE ANALOG INPUTS Internal or external reference can be used for the ADC. In differential mode of operation, there are restrictions on common-mode input signal (V ), which is dependent on the CM reference value and supply voltage ...
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NONVOLATILE FLASH/EE MEMORY The ADuC7019/7020/7021/7022/7024/7025/7026/7027 incorporate Flash/EE memory technology on-chip to provide the user with nonvolatile, in-circuit reprogrammable memory space. Like EEPROM, flash memory can be programmed in-system at a byte level, although it must first be erased. The erase ...
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ADuC7019/20/21/22/24/25/26/ possible to write to a single Flash/EE location address twice single address is written to more than twice, then the data within the Flash/EE memory can be corrupted. That is possible to walk ...
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FEECON is an 8-bit command register. The commands are described in Table 21. Table 21. Command Codes in FEECON Code Command Description 1 0x00 Null Idle State. 1 0x01 Single Read Load FEEDAT with the 16-bit data. Indexed by FEEADR. ...
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ADuC7019/20/21/22/24/25/26/27 EXECUTION TIME FROM SRAM AND FLASH/EE Execution from SRAM Fetching instructions from SRAM takes one clock cycle as the access time of the SRAM and a clock cycle minimum. However, if the instruction ...
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Reset Operation There are four kinds of reset: external, power-on, watchdog expiation, and software force. The RSTSTA register indicates the source of the last reset, and RSTCLR allows clearing the RSTSTA register. These registers can be used during a reset ...
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ADuC7019/20/21/22/24/25/26/27 OTHER ANALOG PERIPHERALS DAC The ADuC7019/7020/7021/7022/7024/7025/7026/7027 incorporate two, three, or four 12-bit voltage output DACs on- chip depending on the model. Each DAC has a rail-to-rail voltage output buffer capable of driving 5 kΩ/100 pF. Each DAC has three ...
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Linearity degradation near ground and V saturation of the output amplifier, and a general representation of its effects (neglecting offset and gain error) is illustrated in Figure 52. The dotted line in Figure 52 indicates the ideal transfer function, and ...
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ADuC7019/20/21/22/24/25/26/27 COMPARATOR The ADuC7019/7020/7021/7022/7024/7025/7026/7027 integrate voltage comparators. The positive input is multiplexed with ADC2 and the negative input has two options: ADC3 or DAC0. The output of the comparator can be configured to generate a system interrupt, can be routed ...
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OSCILLATOR AND PLL—POWER CONTROL Clocking System Each ADuC7019/7020/7021/7022/7024/7025/7026/7027 integrates a 32.768 kHz ±3% oscillator, a clock divider, and a PLL. The PLL locks onto a multiple (1275) of the internal oscillator or an external 32.768 kHz crystal to provide a ...
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ADuC7019/20/21/22/24/25/26/27 MMRs and Keys The operating mode, clocking mode, and programmable clock divider are controlled via two MMRs, PLLCON (see Table 32) and POWCON (see Table 33). PLLCON controls the operating mode of the clock system, while POWCON controls the ...
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DIGITAL PERIPHERALS THREE-PHASE PWM Each ADuC7019/7020/7021/7022/7024/7025/7026/7027 provides a flexible and programmable, three-phase pulse-width modulation (PWM) waveform generator. It can be programmed to generate the required switching patterns to drive a three- phase voltage source inverter for ac induction motor control ...
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ADuC7019/20/21/22/24/25/26/27 40-Pin Package Devices On the 40-pin package devices, the PWM outputs are not directly accessible, as described in the General-Purpose Input/Output section. One channel can be brought out on a GPIO via the PLA as shown in this example: ...
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Three-Phase Timing Unit PWM Switching Frequency (PWMDAT0 MMR) The PWM switching frequency is controlled by the PWM period register, PWMDAT0. The fundamental timing unit of the PWM controller 1/f CORE CORE where f is the core frequency ...
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ADuC7019/20/21/22/24/25/26/27 The advantage of double update mode is that lower harmonic voltages can be produced by the PWM process and faster control bandwidths are possible. However, for a given PWM switching frequency, the PWMSYNC pulses occur at twice the rate ...
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In general, the on-times of the PWM signals in double update mode can be defined as follows: On the high side (PWMDAT0 + PWMDAT0 1 0HH PWMCH0 − PWMDAT1 − PWMDAT1 (PWMDAT0 /2 ...
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ADuC7019/20/21/22/24/25/26/27 This situation is illustrated in Figure 59, where it can be seen that both the 0H and 1L signals are identical, because PWMCH0 = PWMCH1 and the crossover bit for phase B is set. PWMCH0 = PWMCH0 = PWMCH1 ...
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PWM MMRs Interface The PWM block is controlled via the MMRs described in this section. PWMCON Register Name Address Default Value PWMCON 0xFFFFFC00 0x0000 PWMCON is a control register that enables the PWM and chooses the update rate. Table 35. ...
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ADuC7019/20/21/22/24/25/26/27 PWMDAT0 Register Name Address Default Value PWMDAT0 0xFFFFFC08 0x0000 PWMDAT0 is an unsigned 16-bit register for switching period. PWMDAT1 Register Name Address Default Value PWMDAT1 0xFFFFFC0C 0x0000 PWMDAT1 is an unsigned 10-bit register for dead time. PWMCHx Registers Name ...
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GPxCON are the port x control registers, which select the function of each pin of port x. as described in Table 40. Table 40. GPxCON MMR Bit Descriptions Bit Description 31:30 Reserved 29:28 Select Function of Px.7 Pin 27:26 Reserved ...
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ADuC7019/20/21/22/24/25/26/27 SERIAL PORT MUX The serial port mux multiplexes the serial port peripherals 2 (an SPI, UART, and two I Cs) and the programmable logic array (PLA set of ten GPIO pins. Each pin must be configured to ...
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Error = 0% compared to 6.25% with the normal baud rate generator. UART Registers Definition The UART interface consists on 12 registers: COMTX, COMRX, COMDIV0, COMIEN0, COMDIV1, COMIIDO, COMCON0, COMCON1, COMSTA0, COMSTA1, COMSCR, and COMDIV2. COMTX Register Name Address Default ...
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ADuC7019/20/21/22/24/25/26/27 COMCON1 Register Name Address Default Value COMCON1 0xFFFF0710 0x00 COMCON1 is the modem control register. Table 51. COMCON1 MMR Bit Descriptions Bit Name Description 7:5 Reserved. 4 LOOPBACK Loop Back. Set by user to enable loop back mode. In ...
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Network Addressable UART Mode This mode connects the MicroConverter to a 256-node serial network, either as a hardware single-master or via software in a multimaster network. Bit 7 of COMIEN1 (ENAM bit) must be set to enable UART in network ...
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ADuC7019/20/21/22/24/25/26/27 SCL (Serial Clock) I/O Pin The master serial clock (SCL) is used to synchronize the data being transmitted and received through the MOSI SCL period. Therefore, a byte is transmitted/received after eight SCL periods. The SCL pin is configured ...
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ADuC7019/20/21/22/24/25/26/27 Table 59. SPICON MMR Bit Descriptions Bit Description 15:13 Reserved. 12 Continuous Transfer Enable. Set by user to enable continuous transfer. In master mode, the transfer continues until no valid data is available in the TX register ...
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ADuC7019/20/21/22/24/25/26/ Registers 2 The I C peripheral interface consists of 18 MMRs, which are discussed in this section. I2CxMSTA Registers Name Address Default Value I2C0MSTA 0xFFFF0800 0x00 I2C1MSTA 0xFFFF0900 0x00 I2CxMSTA are status registers for the master ...
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I2CxSRX Registers Name Address Default Value I2C0SRX 0xFFFF0808 0x00 I2C1SRX 0xFFFF0908 0x00 I2CxSRX are receive registers for the slave channel. I2CxSTX Registers Name Address Default Value I2C0STX 0xFFFF080C 0x00 I2C1STX 0xFFFF090C 0x00 I2CxSTX are transmit registers for the slave channel. ...
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Table 62. I2C0CFG MMR Bit Descriptions Bit Description 31:5 Reserved. These bits should be written by the user Enable Stop Interrupt. Set by the user to generate an interrupt upon receiving a stop condition and after receiving ...
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Table 63. I2C0FSTA MMR Bit Descriptions Bit Value Description 15:0 Reserved. 9 Master Transmit FIFO Flush. Set by the user to flush the master Tx FIFO. Cleared automatically once the master Tx FIFO is flushed. This bit also flushes the ...
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ADuC7019/20/21/22/24/25/26/27 PLAELMx are Element 0 to Element 15 control registers. They configure the input and output mux of each element, select the function in the look-up table, and bypass/use the flip-flop. See Table 65 and Table 67. Table 65. PLAELMx ...
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PLAIRQ Register Name Address Default Value PLAIRQ 0xFFFF0B44 0x00000000 PLAIRQ enables IRQ0 and/or IRQ1 and selects the source of the IRQ. Table 68. PLAIRQ MMR Bit Descriptions Bit Value Description 15:13 Reserved. 12 PLA IRQ1 Enable Bit. Set by user ...
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ADuC7019/20/21/22/24/25/26/27 PROCESSOR REFERENCE PERIPHERALS INTERRUPT SYSTEM There are 23 interrupt sources on the ADuC7019/7020/ 7021/7022/7024/7025/7026/7027 that are controlled by the interrupt controller. Most interrupts are generated from the on- chip peripherals, such as ADC and UART. Four additional interrupt sources ...
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FIQSTA Register Name Address Default Value FIQSTA 0xFFFF0100 0x00000000 FIQSIG Register Name Address Default Value FIQSIG 0xFFFF0104 0x00XXX000 FIQEN Register Name Address Default Value FIQEN 0xFFFF0108 0x00000000 FIQCLR Register Name Address Default Value FIQCLR 0xFFFF010C 0x00000000 Bit 31 to Bit ...
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ADuC7019/20/21/22/24/25/26/27 Timer0 (RTOS Timer) Timer0 is a general-purpose, 16-bit timer (count-down) with a programmable prescaler (see Figure 63). The prescaler source is the core clock frequency (HCLK) and can be scaled by factors of 1, 16, or 256. 16-BIT LOAD ...
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Table 75. T1CON MMR Bit Descriptions Bit Value Description 31:18 Reserved. 17 Event Select Bit. Set by user to enable time capture of an event. Cleared by user to disable time capture of an event 16:12 Event Select Range, 0 ...
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ADuC7019/20/21/22/24/25/26/27 T2CON Register Name Address Default Value T2CON 0xFFFF0348 0x0000 T2CON is the configuration MMR described in Table 76. Table 76. T2CON MMR Bit Descriptions Bit Value Description 31:11 Reserved. 10:9 Clock Source. 00 External Crystal. 01 External Crystal. 10 ...
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Table 77. T3CON MMR Bit Descriptions Bit Value Description 31:9 Reserved. 8 Count Up. Set by user for Timer3 to count up. Cleared by user for Timer3 to count down by default. 7 Timer3 Enable Bit. Set by user to ...
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ADuC7019/20/21/22/24/25/26/27 ADuC7026/ ADuC7027 A16 AD15:0 LATCH AE MS0 MS1 WS RS Figure 68. Interfacing to External EPROM/RAM XMCFG Register Name Address Default Value XMCFG 0xFFFFF000 0x00 XMCFG is set enable external memory access. This must be set ...
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MCLK AD16:0 ADDRESS MSx AE RS Figure 69. External Memory Read Cycle MCLK AD16:0 ADDRESS EXTRA ADDRESS HOLD TIME (BIT-10) MSx AE RS Figure 70. External Memory Read Cycle with Address Hold and Bus Turn Cycles Rev Page ...
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ADuC7019/20/21/22/24/25/26/27 MCLK AD16:0 MSx AE WS Figure 71. External Memory Write Cycle with Address and Write Hold Cycles MCLK AD16:0 MSx AE WS ADDRESS EXTRA ADDRESS HOLD TIME (BIT-10) WRITE HOLD ADDRESS AND DATA CYCLES (BIT-8) ADDRESS 1 ADDRESS WAIT ...
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HARDWARE DESIGN CONSIDERATIONS POWER SUPPLIES The ADuC7019/7020/7021/7022/7024/7025/7026/7027 operational power supply voltage range is 2 3.6 V. Separate analog and digital power supply pins (AV IOV , respectively) allow kept relatively free noisy ...
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ADuC7019/20/21/22/24/25/26/27 GROUNDING AND BOARD LAYOUT RECOMMENDATIONS As with all high resolution data converters, special attention must be paid to grounding and PC board layout of ADuC7019/7020/7021/7022/7024/7025/7026/7027-based designs in order to achieve optimum performance from the ADCs and DAC. Although the ...
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POWER-ON RESET OPERATION An internal power-on reset (POR) is implemented on the ADuC7019/7020/7021/7022/7024/7025/7026/7027. For LV below 2.35 V typical, the internal POR holds the part in reset rises above 2. internal timer times out for DD ...
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ADuC7019/20/21/22/24/25/26/27 DEVELOPMENT TOOLS PC-BASED TOOLS Four types of development systems are available for the ADuC7019/7020/7021/7022/7024/7025/7026/7027 family: • The ADuC7026 QuickStart Plus is intended for new users who want to have a comprehensive hardware development environment. Since the ADuC7026 contains the ...
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OUTLINE DIMENSIONS PIN 1 INDICATOR 12° MAX 1.00 0.85 0.80 SEATING PLANE 9.00 BSC SQ PIN 1 INDICATOR TOP VIEW 1.00 12° MAX 0.85 0.80 SEATING PLANE 6.00 BSC SQ 0.60 MAX 0.50 TOP BSC 5.75 VIEW BCS SQ 0.50 ...
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ADuC7019/20/21/22/24/25/26/27 1.45 1.40 1.35 SEATING PLANE VIEW A ROTATED 90° CCW 1.45 1.40 1.35 0.15 0.05 VIEW A ROTATED 90° CCW 0.75 0.60 1.60 MAX 0. PIN 1 0.20 0.09 7° 3.5° 16 0° 17 0.08 MAX COPLANARITY ...
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ORDERING GUIDE ADC DAC Model Channels Channels 1 2 ADuC7019BCPZ62I ADuC7019BCPZ62I- ADuC7019BCPZ62IRL7 ADuC7020BCPZ62 1 ADuC7020BCPZ62- ADuC7020BCPZ62 RL7 ADuC7020BCPZ62I 1 ...
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... ADuC7019/20/21/22/24/25/26/27 ADC DAC Model Channels Channels 1 12 ADuC7025BCPZ62 1 ADuC7025BCPZ62-RL 12 ADuC7025BCPZ62 RL7 1 12 ADuC7025BCPZ32 1 ADuC7025BCPZ32-RL 12 ADuC7025BCPZ32 RL7 1 12 ADuC7025BSTZ62 1 ADuC7025BSTZ62- ADuC7026BSTZ62 1, 3 ADuC7026BSTZ62- ADuC7026BSTZ62I 1, ADuC7026BSTZ62I- ADuC7027BSTZ62 ADuC7027BSTZ62-RL EVAL-ADuC7020MK EVAL-ADuC7020QS EVAL-ADuC7024QS EVAL-ADuC7026QS ...
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NOTES ADuC7019/20/21/22/24/25/26/27 Rev Page ...
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ADuC7019/20/21/22/24/25/26/27 NOTES 2 Purchase of licensed I C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I 2 Rights to use these components system, ...