ADUC7025BCPZ32-RL7 AD [Analog Devices], ADUC7025BCPZ32-RL7 Datasheet - Page 54

• Manufacturer Part Number: ADUC7025BCPZ32-RL7
• Description: Precision Analog Microcontroller 12-bit Analog I/O, ARM7TDMI MCU
• Manufacturer: AD [Analog Devices]

ADuC7019/20/21/22/24/25/26/27
40-Pin Package Devices
On the 40-pin package devices, the PWM outputs are not
directly accessible, as described in the General-Purpose
Input/Output section. One channel can be brought out on a
GPIO via the PLA as shown in this example:
PWMCON = 0x1;
PWMDAT0 = 0x055F;
// Configure Port Pins
GP4CON = 0x300;
GP3CON = 0x1;
// PWM0 onto P4.2
PLAELM8 = 0x0035;
PLAELM10 = 0x0059;
Description of the PWM Block
Figure 56. The generation of the six output PWM signals on
pins PWM0
•
The Three-Phase PWM Timing Unit. The core of the PWM
controller, it generates three pairs of complemented and dead-
time-adjusted, center-based PWM signals.
A functional block diagram of the PWM controller is shown in
H
to PWM2
L
is controlled by four important blocks:
TO INTERRUPT
CONTROLLER
// enables PWM o/p
// PWM switching freq
// P4.2 as PLA output
// P3.0 configured as
// output of PWM0
//(internally)
// P3.0 (PWM output)
// input of element 8
// PWM from element 8
CORE CLOCK
CONTROLLER
SHUTDOWN
PWM
CONFIGURATION
Figure 56. Overview of the PWM Controller
REGISTERS DUTY CYCLE
PWMDAT0
PWMDAT1
PWMDAT2
PWMCON
THREE-PHASE
PWM TIMING
Rev. A | Page 54 of 92
UNIT
REGISTERS
PWMCH0
PWMCH1
PWMCH2
SYNC
•
•
•
The PWMSYNC pulse control unit generates the internal
synchronization pulse and also controls whether the external
PWM
The PWM controller is driven by the ADuC7019/7020/
7021/7022/7024/7025/7026/7027 core clock frequency and is
capable of generating two interrupts to the ARM core. One
interrupt is generated on the occurrence of a PWMSYNC pulse,
and the other is generated on the occurrence of any PWM
shutdown action.
CONTROL
OUTPUT
PWMEN
UNIT
The Output Control Unit. This block can redirect the
outputs of the three-phase timing unit for each channel to
either the high-side or low-side output. In addition, the
output control unit allows individual enabling/disabling of
each of the six PWM output signals.
The Gate Drive Unit. This block can generate the high
frequency chopping frequency and its subsequent mixing
with the PWM signals.
The PWM Shutdown Controller. This block takes care of
the PWM shutdown via the PWM
correct reset signal for the timing unit.
SYNC
pin is used or not.
PWMCFG
DRIVE
GATE
UNIT
PWM0
PWM0
PWM1
PWM1
PWM2
PWM2
PWM
PWM
SYNC
TRIP
H
L
H
L
H
L
TRIP
pin and generates the