ADUC7025BCPZ32-RL7 AD [Analog Devices], ADUC7025BCPZ32-RL7 Datasheet - Page 74

• Manufacturer Part Number: ADUC7025BCPZ32-RL7
• Description: Precision Analog Microcontroller 12-bit Analog I/O, ARM7TDMI MCU
• Manufacturer: AD [Analog Devices]

ADuC7019/20/21/22/24/25/26/27
PROCESSOR REFERENCE PERIPHERALS
INTERRUPT SYSTEM
There are 23 interrupt sources on the ADuC7019/7020/
7021/7022/7024/7025/7026/7027 that are controlled by the
interrupt controller. Most interrupts are generated from the on-
chip peripherals, such as ADC and UART. Four additional
interrupt sources are generated from external interrupt request
pins, IRQ0, IRQ1, IRQ2, and IRQ3. The ARM7TDMI CPU core
only recognizes interrupts as one of two types, a normal
interrupt request IRQ or a fast interrupt request FIQ. All the
interrupts can be masked separately.
The control and configuration of the interrupt system is
managed through nine interrupt-related registers, four
dedicated to IRQ, and four dedicated to FIQ. An additional
MMR is used to select the programmed interrupt source. The
bits in each IRQ and FIQ registers (except for Bit 23) represent
the same interrupt source as described in Table 72.
Table 72. IRQ/FIQ MMRs Bit Description
Bit
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
IRQ
The interrupt request (IRQ) is the exception signal to enter the
IRQ mode of the processor. It is used to service general-
purpose interrupt handling of internal and external events.
The four 32-bit registers dedicated to IRQ are: IRQSTA,
IRQSIG, IRQEN, and IRQCLR.
Description
All Interrupts OR’ed
SWI
Timer0
Timer1
Wake-Up Timer – Timer2
Watchdog Timer – Timer3
Flash Control
ADC Channel
PLL Lock
I2C0 Slave
I2C0 Master
I2C1 Master
SPI Slave
SPI Master
UART
External IRQ0
Comparator
PSM
External IRQ1
PLA IRQ0
PLA IRQ1
External IRQ2
External IRQ3
PWM Trip (IRQ only)/ PWM Sync (FIQ only)
Rev. A | Page 74 of 92
IRQSTA Register
Name
IRQSTA
IRQSTA (read-only register) provides the current enabled IRQ
source status. When set to 1 that source should generate an
active IRQ request to the ARM7TDMI core. There is no priority
encoder or interrupt vector generation. This function is
implemented in software in a common interrupt handler
routine. All 32 bits are logically OR’ e d to create the IRQ signal
to the ARM7TDMI core.
IRQSIG Register
Name
IRQSIG
IRQSIG reflects the status of the different IRQ sources. If a
peripheral generates an IRQ signal, then the corresponding bit
in the IRQSIG is set; otherwise it is cleared. The IRQSIG bits are
cleared when the interrupt in the particular peripheral is
cleared. All IRQ sources can be masked in the IRQEN MMR.
IRQSIG is read-only.
IRQEN Register
Name
IRQEN
IRQEN provides the value of the current enable mask. When bit
is set to 1, the source request is enabled to create an IRQ
exception. When bit is set to 0, the source request is disabled or
masked, which does not create an IRQ exception.
IRQCLR Register
Name
IRQCLR
IRQCLR (write-only register) clears the IRQEN register in
order to mask an interrupt source. Each bit set to 1 clears the
corresponding bit in the IRQEN register without affecting the
remaining bits. The pair of registers, IRQEN and IRQCLR,
independently manipulates the enable mask without requiring
an atomic read-modify-write.
FIQ
The fast interrupt request (FIQ) is the exception signal to enter
the FIQ mode of the processor. It is provided to service data
transfer or communication channel tasks with low latency. The
FIQ interface is identical to the IRQ interface providing the
second-level interrupt (highest priority). Four 32-bit registers
are dedicated to FIQ: FIQSIG, FIQEN, FIQCLR, and FIQSTA.
Address
0xFFFF0000
Address
0xFFFF0004
Address
0xFFFF0008
Address
0xFFFF000C
Default Value
0x00000000
Default Value
0x00XXX000
Default Value
0x00000000
Default Value
0x00000000
Access
R
Access
R
Access
R/W
Access
W