ADUC7025BCPZ32-RL7 AD [Analog Devices], ADUC7025BCPZ32-RL7 Datasheet - Page 44

• Manufacturer Part Number: ADUC7025BCPZ32-RL7
• Description: Precision Analog Microcontroller 12-bit Analog I/O, ARM7TDMI MCU
• Manufacturer: AD [Analog Devices]

ADuC7019/20/21/22/24/25/26/27
It is possible to write to a single Flash/EE location address
twice. If a single address is written to more than twice, then the
data within the Flash/EE memory can be corrupted. That is, it is
possible to walk zeros only byte wise.
SECURITY
The 62 kB of Flash/EE memory available to the user can be read
and write protected.
Bit 31 of the FEEPRO/FEEHIDE MMR (see Table 22) protects
the 62 kB from being read through JTAG and also in parallel
programming mode. The other 31 bits of this register protect
writing to the flash memory. Each bit protects four pages, that
is, 2 kB. Write protection is activated for all types of access.
Three Levels of Protection
•
•
•
Sequence to Write the Key
1.
2.
3.
4.
5.
To remove or modify the protection, the same sequence is used
with a modified value of FEEPRO. If the key chosen is the value
0×DEAD, then the memory protection cannot be removed. Only a
mass erase unprotects the part, but it also erases all user code.
The sequence to write the key is illustrated in the following
example (this protects writing Pages 4 to 7 of the Flash):
FEEPRO=0xFFFFFFFD;
FEEMOD=0x48;
FEEADR=0x1234;
FEEDAT=0x5678;
FEECON= 0x0C;
The same sequence should be followed to protect the part
permanently with FEEADR = 0×DEAD and FEEDAT =
0×DEAD.
Protection can be set and removed by writing directly into
FEEHIDE MMR. This protection does not remain after reset.
Protection can be set by writing into FEEPRO MMR. It
only takes effect after a save protection command (0×0C)
and a reset. The FEEPRO MMR is protected by a key to
avoid direct access. The key is saved once and must be
entered again to modify FEEPRO. A mass erase sets the
key back to 0×FFFF but also erases all the user code.
Flash can be permanently protected by using the FEEPRO
MMR and a particular value of key: 0×DEADDEAD.
Entering the key again to modify the FEEPRO register is
not allowed.
Write the bit in FEEPRO corresponding to the page to be
protected.
Enable key protection by setting Bit 6 of FEEMOD (Bit 5
must equal 0).
Write a 32-bit key in FEEADR, FEEDAT.
Run the write key command 0×0C in FEECON; wait for
the read to be successful by monitoring FEESTA.
Reset the part.
//Protect pages 4 to 7
//Write key enable
//16 bit key value
//16 bit key value
// Write key command
Rev. A | Page 44 of 92
FLASH/EE CONTROL INTERFACE
Serial, parallel, and JTAG programming use the Flash/EE control
interface, which includes eight MMRs outlined in this section.
FEESTA Register
Name
FEESTA
FEESTA is a read-only register that reflects the status of the
flash control interface as described in Table 19.
Table 19. FEESTA MMR Bit Designations
Bit
15:6
5
4
3
2
1
0
FEEMOD Register
Name
FEEMOD
FEEMOD sets the operating mode of the flash control interface.
Table 20 shows FEEMOD MMR bit designations.
Table 20. FEEMOD MMR Bit Designations
Bit
15:9
8
7:5
4
3
2:0
FEECON Register
Name
FEECON
Description
Reserved.
Burst Command Enable. Set when the command is a
burst command: 0x07, 0x08, or 0x09. Cleared when
another command.
Reserved.
Flash Interrupt Status Bit. Set automatically when an
interrupt occurs, that is, when a command is complete
and the Flash/EE interrupt enable bit in the FEEMOD
register is set. Cleared when reading FEESTA register.
Flash/EE Controller Busy. Set automatically when the
controller is busy. Cleared automatically when the
controller is not busy.
Command Fail. Set automatically when a command
completes unsuccessfully. Cleared automatically when
reading FEESTA register.
Command Pass. Set by MicroConverter when a
command completes successfully. Cleared
automatically when reading FEESTA register.
Description
Reserved.
Reserved. This bit should always be set to 0.
Reserved. These bits should always be set to 0 except
when writing keys. See the Sequence to Write the Key
section.
Flash/EE Interrupt Enable. Set by user to enable the
Flash/EE interrupt. The interrupt occurs when a
command is complete. Cleared by user to disable
the Flash/EE interrupt.
Erase/Write Command Protection. Set by user to
enable the erase and write commands. Cleared to
protect the Flash against erase/write command.
Reserved. These bits should always be set to 0.
Address
0xFFFFF800
Address
0xFFFFF804
Address
0xFFFFF808
Default Value
0x20
Default Value
0x0000
Default Value
0x07
Access
R
Access
R/W
Access
R/W