ADUC7025BCPZ32-RL7 AD [Analog Devices], ADUC7025BCPZ32-RL7 Datasheet - Page 73
ADUC7025BCPZ32-RL7
Manufacturer Part Number
ADUC7025BCPZ32-RL7
Description
Precision Analog Microcontroller 12-bit Analog I/O, ARM7TDMI MCU
Manufacturer
AD [Analog Devices]
Datasheet
1.ADUC7025BCPZ32-RL7.pdf
(92 pages)
- Current page: 73 of 92
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PLAIRQ Register
Name
PLAIRQ
PLAIRQ enables IRQ0 and/or IRQ1 and selects the source of
the IRQ.
Table 68. PLAIRQ MMR Bit Descriptions
Bit
15:13
12
11:8
7:5
4
3:0
PLAADC Register
Name
PLAADC
PLAADC is a PLA source from the ADC start conversion
signal.
Table 69. PLAADC MMR Bit Descriptions
Bit
31:5
4
3:0
Value
0000
0001
1111
Value
0000
0001
1111
0000
0001
1111
Address
0xFFFF0B44
Address
0xFFFF0B48
Description
Reserved.
ADC Start Conversion Enable Bit. Set by user
to enable ADC start conversion from PLA.
Cleared by user to disable ADC start
conversion from PLA.
ADC Start Conversion Source.
PLA Element 0.
PLA Element 1.
PLA Element 15.
Description
Reserved.
PLA IRQ1 Enable Bit. Set by user to enable
IRQ1 output from PLA. Cleared by user to
disable IRQ1 output from PLA.
PLA IRQ1 Source.
PLA Element 0.
PLA Element 1.
PLA Element 15.
Reserved.
PLA IRQ0 Enable Bit. Set by user to enable
IRQ0 output from PLA. Cleared by user to
disable IRQ0 output from PLA.
PLA IRQ0 Source.
PLA Element 0.
PLA Element 1.
PLA Element 15.
Default Value
0x00000000
Default Value
0x00000000
Access
R/W
Access
R/W
Rev. A | Page 73 of 92
PLADIN Register
Name
PLADIN
PLADIN is a data input MMR for PLA.
Table 70. PLADIN MMR Bit Descriptions
Bit
31:16
15:0
PLADOUT Register
Name
PLADOUT
PLADOUT is a data output MMR for PLA. This register is
always updated.
Table 71. PLADOUT MMR Bit Descriptions
Bit
31:16
15:0
PLALCK Register
Name
PLALCK
PLALCK is a PLA lock option. Bit 0 is written only once. When
set, it does not allow modifying any of the PLA MMR, except
PLADIN. A PLA tool is provided in the development system to
easily configure the PLA.
ADuC7019/20/21/22/24/25/26/27
Description
Reserved
Output Bit from Element 15 to Element 0
Address
0xFFFF0B4C
Address
0xFFFF0B50
Address
0xFFFF0B54
Description
Reserved
Input Bit to Element 15 to Element 0
Default Value
0x00000000
Default Value
0x00000000
Default Value
0x00
Access
R/W
Access
R
Access
W
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