ADUC7025BCPZ32-RL7 AD [Analog Devices], ADUC7025BCPZ32-RL7 Datasheet - Page 62

• Manufacturer Part Number: ADUC7025BCPZ32-RL7
• Description: Precision Analog Microcontroller 12-bit Analog I/O, ARM7TDMI MCU
• Manufacturer: AD [Analog Devices]

ADuC7019/20/21/22/24/25/26/27
SERIAL PORT MUX
The serial port mux multiplexes the serial port peripherals
(an SPI, UART, and two I
(PLA) to a set of ten GPIO pins. Each pin must be configured to
one of its specific I/O functions as described in Table 45.
Table 45. SPM Configuration
Pin
SPM0
SPM1
SPM2
SPM3
SPM4
SPM5
SPM6
SPM7
SPM8
SPM9
Table 45 also details the mode for each of the SPMUX GPIO
pins. This configuration has to be done via the GP0CON,
GP1CON, and GP2CON MMRs. By default these ten pins are
configured as GPIOs.
UART SERIAL INTERFACE
The UART peripheral is a full-duplex, universal, asynchronous
receiver/transmitter. It is fully compatible with the 16450 serial port
standard. The UART performs serial-to-parallel conversion on data
characters received from a peripheral device or modem, and
parallel-to-serial conversion on data characters received from the
CPU. The UART includes a fractional divider for baud rate
generation and has a network addressable mode. The UART
function is made available on the 10 pins of the ADuC7019/7020/
7021/7022/7024/7025/7026/7027 (see Table 46).
Table 46. UART Signal Description
Pin
SPM0 (Mode 1)
SPM1 (Mode 1)
SPM2 (Mode 1)
SPM3 (Mode 1)
SPM4 (Mode 1)
SPM5 (Mode 1)
SPM6 (Mode 1)
SPM7 (Mode 1)
SPM8 (Mode 2)
SPM9 (Mode 2)
The serial communication adopts an asynchronous protocol,
which supports various word lengths, stop bits, and parity
generation options selectable in the configuration register.
GPIO
(00)
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P0.7
P2.0
UART
(01)
SIN
SOUT
RTS
CTS
RI
DCD
DSR
DTR
ECLK/XCLK
CONV
Signal
SIN
SOUT
RTS
CTS
RI
DCD
DSR
DTR
SIN
SOUT
2
Cs) and the programmable logic array
UART/I
(10)
SPICSL
SOUT
I2C0SCL
I2C0SDA
I2C1SCL
I2C1SDA
SPICLK
SPIMISO
SPIMOSI
SIN
Description
Serial Receive Data
Serial Transmit Data
Request to Send
Clear to Send
Ring Indicator
Data Carrier Detect
Data Set Ready
Data Terminal Ready
Serial Receive Data
Serial Transmit Data
2
C/SPI
PLA
(11)
PLAI[0]
PLAI[1]
PLAI[2]
PLAI[3]
PLAI[4]
PLAI[5]
PLAI[6]
PLAO[0]
PLAO[4]
PLAO[5]
Rev. A | Page 62 of 92
Baud Rate Generation
There are two ways of generating the UART baud rate.
1. Normal 450 UART Baud Rate Generation.
The baud rate is a divided version of the core clock using the
value in COMDIV0 and COMDIV1 MMRs (16-bit value, DL).
Table 47 gives some common baud rate values.
Table 47. Baud Rate Using the Normal Baud Rate Generator
Baud Rate
9600
19200
115200
9600
19200
115200
2. Using the Fractional Divider.
The fractional divider combined with the normal baud rate
generator produces a wider range of more accurate baud rates.
Calculation of the baud rate using fractional divider is as
follows:
For example, generation of 19,200 baud with CD bits = 3
(Table 47 gives DL = 8 h),
where:
M = 1
N = 0.06 × 2048 = 128
where:
Baud Rate = 19,200 bps
Baud
Baud
M
M
M
Baud
+
+
+
CLOCK
2048
2048
2048
CORE
N
Rate
Rate
N
N
rate
=
=
=
=
=
. 1
Baud
19200
CD
0
0
0
3
3
3
Figure 61. Baud Rate Generation Options
2
2
=
06
3
/(M+N/2048)
CD
×
2
16
41
×
CD
Rate
×
16
41
/2
.
×
78
2
41
8
41
3
.
×
×
78
DL
88 h
44 h
0B h
11 h
8 h
1 h
×
×
MHz
41
×
DL
.
.
16
16
78
78
MHz
2
2
.
×
78
×
CD
MHz
×
×
MHz
⎛
⎜
⎝
2
8
MHz
×
2048
×
×
128
2
16
FBEN
(
2
×
M
Actual Baud Rate
9600
19200
118691
9600
20400
163200
×
DL
⎞
⎟
⎠
DL
+
2048
×
N
2
)
/16DL
UART
% Error
0
0
3
0
6.25
41.67