ADUC7025BCPZ32-RL7 AD [Analog Devices], ADUC7025BCPZ32-RL7 Datasheet - Page 50

• Manufacturer Part Number: ADUC7025BCPZ32-RL7
• Description: Precision Analog Microcontroller 12-bit Analog I/O, ARM7TDMI MCU
• Manufacturer: AD [Analog Devices]

ADuC7019/20/21/22/24/25/26/27
COMPARATOR
The ADuC7019/7020/7021/7022/7024/7025/7026/7027
integrate voltage comparators. The positive input is multiplexed
with ADC2 and the negative input has two options: ADC3 or
DAC0. The output of the comparator can be configured to
generate a system interrupt, can be routed directly to the
programmable logic array, can start an ADC conversion, or can
be on an external pin, CMP
Hysteresis
Figure 54 shows how the input offset voltage and hysteresis
terms are defined. Input offset voltage (V
between the center of the hysteresis range and the ground level.
This can either be positive or negative. The hysteresis voltage
(V
Comparator Interface
The comparator interface consists of a 16-bit MMR, CMPCON,
which is described in Table 29.
CMPCON Register
Name
CMPCON
H
) is ½ the width of the hysteresis range.
P0.0/CMP
ADC2/CMP0
ADC3/CMP1
Figure 54. Comparator Hysteresis Transfer Function
COMP
Address
0xFFFF0444
OUT
OUT
DAC0
V
Figure 53. Comparator
OS
V
H
OUT
MUX
, as shown in Figure 53.
V
Default Value
0x0000
H
OS
COMP0
) is the difference
MUX
IRQ
Access
R/W
Rev. A | Page 50 of 92
Table 29. CMPCON MMR Bit Descriptions
Bit
15:11
10
9:8
7:6
5
4:3
2
1
0
Value
00
01
10
11
00
01
10
11
00
11
Name
CMPEN
CMPIN
CMPOC
CMPOL
CMPRES
CMPHYST
CMPORI
CMPOFI
Description
Reserved.
Comparator Enable Bit. Set by user
to enable the comparator. Cleared
by user to disable the comparator.
Comparator Negative Input Select
Bits.
AVDD/2.
ADC3 input.
DAC0 output.
Reserved.
Comparator Output Configuration
Bits.
Reserved.
Reserved.
Output on CMP
IRQ.
Comparator Output Logic State Bit.
When low, the comparator output is
high if the positive input (CMP0) is
above the negative input (CMP1).
When high, the comparator output
is high if the positive input is below
the negative input.
Response Time.
5 μs response time typical for large
signals (2.5 V differential).
17 μs response time typical for small
signals (0.65 mV differential).
3 μs typical.
Comparator Hysteresis Bit. Set by
user to have a hysteresis of about
7.5 mV. Cleared by user to have no
hysteresis.
Comparator Output Rising Edge
Interrupt. Set automatically when a
rising edge occurs on the moni-
tored voltage (CMP0). Cleared by
user by writing a 1 to this bit.
Comparator Output Falling Edge
Interrupt. Set automatically when a
falling edge occurs on the monitored
voltage (CMP0). Cleared by user.
OUT
.