ADUC7025BCPZ32-RL7 AD [Analog Devices], ADUC7025BCPZ32-RL7 Datasheet - Page 66

• Manufacturer Part Number: ADUC7025BCPZ32-RL7
• Description: Precision Analog Microcontroller 12-bit Analog I/O, ARM7TDMI MCU
• Manufacturer: AD [Analog Devices]

ADuC7019/20/21/22/24/25/26/27
SCL (Serial Clock) I/O Pin
The master serial clock (SCL) is used to synchronize the data
being transmitted and received through the MOSI SCL period.
Therefore, a byte is transmitted/received after eight SCL
periods. The SCL pin is configured as an output in master mode
and as an input in slave mode.
In master mode, polarity and phase of the clock are controlled
by the SPICON register, and the bit rate is defined in the
SPIDIV register as follows:
The maximum speed of the SPI clock is dependant on the clock
divider bits and is summarized in Table 57.
Table 57. SPI Speed vs. Clock Divider Bits in Master Mode
CD Bits
SPIDIV in
hex
SPI speed
in MHz
In slave mode, the SPICON register must be configured with
the phase and polarity of the expected input clock. The slave
accepts data from an external master up to 10.4 Mb at CD = 0.
The formula to determine the maximum speed is as follow:
In both master and slave modes, data is transmitted on one edge
of the SCL signal and sampled on the other. Therefore, it is
important that the polarity and phase are configured the same
for the master and slave devices.
Chip Select (CS) Input Pin
In SPI slave mode, a transfer is initiated by the assertion of CS ,
which is an active low input signal. The SPI port then transmits
and receives 8-bit data until the transfer is concluded by
deassertion of CS . In slave mode, CS is always an input.
SPI Registers
The following MMR registers are used to control the SPI
interface: SPISTA, SPIRX, SPITX, SPIDIV, and SPICON.
f
serial
clock
f
serialcloc
0
0x05
3.482
=
2
k
×
=
1 (
1
0x0B
1.741
f
+
HCLK
f
UCLK
4
SPIDIV
2
0x17
0.870
)
3
0x2F
0.435
4
0x5F
0.218
5
0xBF
0.109
Rev. A | Page 66 of 92
SPISTA Register
Name
SPISTA
SPISTA is an 8-bit read-only status register. Only Bit 1 or Bit 4
of this register generates an interrupt. Bit 6 of the SPICON
register determines which bit generates the interrupt.
Table 58. SPISTA MMR Bit Descriptions
Bit
7:6
5
4
3
2
1
0
SPIRX Register
Name
SPIRX
SPIRX is an 8-bit read-only receive register.
SPITX Register
Name
SPITX
SPITX is an 8-bit write-only transmit register.
SPIDIV Register
Name
SPIDIV
SPIDIV is an 8-bit serial clock divider register.
SPICON Register
Name
SPICON
SPICON is a 16-bit control register.
Description
Reserved.
SPIRX Data Register Overflow Status Bit. Set if SPIRX is
overflowing. Cleared by reading SPIRX register.
SPIRX Data Register IRQ. Set automatically if Bit 3 or Bit 5
is set. Cleared by reading SPIRX register.
SPIRX Data Register Full Status Bit. Set automatically if a
valid data is present in the SPIRX register. Cleared by
reading SPIRX register.
SPITX Data Register Underflow Status Bit. Set auto-
matically if SPITX is under flowing. Cleared by writing in
the SPITX register.
SPITX Data Register IRQ. Set automatically if Bit 0 is clear
or Bit 2 is set. Cleared by writing in the SPITX register or if
finished transmission disabling the SPI.
SPITX Data Register Empty Status Bit. Set by writing to
SPITX to send data. This bit is set during transmission of
data. Cleared when SPITX is empty.
Address
0xFFFF0A00
Address
0xFFFF0A04
Address
0xFFFF0A08
Address
0xFFFF0A0C
Address
0xFFFF0A10
Default Value
0x00
Default Value
0x00
Default Value
0x00
Default Value
0x1B
Default Value
0x0000
Access
R/W
Access
R
Access
W
Access
R/W
Access
R/W