ADUC7025BCPZ32-RL7 AD [Analog Devices], ADUC7025BCPZ32-RL7 Datasheet - Page 32

• Manufacturer Part Number: ADUC7025BCPZ32-RL7
• Description: Precision Analog Microcontroller 12-bit Analog I/O, ARM7TDMI MCU
• Manufacturer: AD [Analog Devices]

ADuC7019/20/21/22/24/25/26/27
More information relative to the programmer’s model and the
ARM7TDMI core architecture can be found in the following
documents from ARM:
•
•
USER MODE
DDI0029G, ARM7TDMI Technical Reference Manual
DDI0100E, ARM Architecture Reference Manual
R15 (PC)
CPSR
R10
R11
R12
R13
R14
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
SPSR_FIQ
R10_FIQ
R11_FIQ
R12_FIQ
R13_FIQ
R14_FIQ
R8_FIQ
R9_FIQ
Figure 32. Register Organization
MODE
FIQ
SPSR_SVC
R13_SVC
R14_SVC
MODE
SVC
SPSR_ABT
R13_ABT
R14_ABT
ABORT
MODE
USABLE IN USER MODE
SYSTEM MODES ONLY
SPSR_IRQ
R13_IRQ
R14_IRQ
MODE
IRQ
UNDEFINED
SPSR_UND
R13_UND
R14_UND
MODE
Rev. A | Page 32 of 92
INTERRUPT LATENCY
The worst case latency for a fast interrupt request (FIQ) consists
of the following:
•
•
•
•
At the end of this time, the ARM7TDMI executes the instruc-
tion at 0x1C (FIQ interrupt vector address). The maximum
total time is 50 processor cycles, which is just under 1.2 μs in a
system using a continuous 41.78 MHz processor clock.
The maximum interrupt request (IRQ) latency calculation is
similar, but must allow for the fact that FIQ has higher priority
and could delay entry into the IRQ handling routine for an
arbitrary length of time. This time can be reduced to 42 cycles
if the LDM command is not used. Some compilers have an
option to compile without using this command. Another
option is to run the part in thumb mode, where the time
is reduced to 22 cycles.
The minimum latency for FIQ or IRQ interrupts is a total of
five cycles, which consist of the shortest time the request can
take through the synchronizer, plus the time to enter the
exception mode.
Note that the ARM7TDMI always runs in ARM (32-bit) mode
when in privileged modes, for example, when executing
interrupt service routines.
The longest time the request can take to pass through
the synchronizer
The time for the longest instruction to complete
(the longest instruction is an LDM) that loads all
the registers including the PC
The time for the data abort entry
The time for FIQ entry