ADUC7025BCPZ32-RL7 AD [Analog Devices], ADUC7025BCPZ32-RL7 Datasheet - Page 58

• Manufacturer Part Number: ADUC7025BCPZ32-RL7
• Description: Precision Analog Microcontroller 12-bit Analog I/O, ARM7TDMI MCU
• Manufacturer: AD [Analog Devices]

ADuC7019/20/21/22/24/25/26/27
This situation is illustrated in Figure 59, where it can be seen
that both the 0H and 1L signals are identical, because
PWMCH0 = PWMCH1 and the crossover bit for phase B is set.
In addition, the other four signals (0L, 1H, 2H, and 2L) have
been disabled by setting the appropriate enable/disable bits of
the PWMEN register. In Figure 59, the appropriate value for
the PWMEN register is 0×00A7. In normal ECM operation,
each inverter leg is disabled for certain periods of time so that
the PWMEN register is changed based on the position of the
rotor shaft (motor commutation).
Gate Drive Unit
The gate drive unit of the PWM controller adds features that
simplify the design of isolated gate-drive circuits for PWM
inverters. If a transformer-coupled, power device, gate-drive
amplifier is used, then the active PWM signal must be chopped at
a high frequency. The 10-bit read/write PWMCFG register
programs this high frequency chopping mode. The chopped
active PWM signals can be required for the high-side drivers
only, the low-side drivers only, or both the high-side and low-
side switches. Therefore, independent control of this mode for
both high-side and low-side switches is included with two
separate control bits in the PWMCFG register.
Typical PWM output signals with high frequency chopping
enabled on both high-side and low-side signals are shown in
Figure 60. Chopping of the high-side PWM outputs (0H, 1H,
and 2H) is enabled by setting Bit 8 of the PWMCFG register.
Chopping of the low-side PWM outputs (0L, 1L, and 2L) is
enabled by setting Bit 9 of the PWMCFG register. The high
chopping frequency is controlled by the 8-bit word (GDCLK)
placed in Bit 0 to Bit 7 of the PWMCFG register. The period of
this high frequency carrier is
T
0H
1H
2H
0L
1L
2L
CHOP
Figure 59. Active LO PWM Signals Suitable for ECM Control,
PWMCH0 = PWMCH1, Crossover 1H/1L Pair and Disable
2 × PWMDAT1
= (4 × (GDCLK + 1)) × t
0L, 1H, 2H, and 2L Outputs in Single Update Mode.
PWMDAT0
PWMCH0 =
PWMCH1
PWMCH0 =
PWMCH1
CORE
PWMDAT0
2 × PWMDAT1
Rev. A | Page 58 of 92
The chopping frequency is therefore an integral subdivision of
the MicroConverter core frequency
The GDCLK value can range from 0 to 255, corresponding to
a programmable chopping frequency rate from 40.8 kHz to
10.44 MHz for a 41.78 MHz core frequency. The gate drive
features must be programmed before operation of the PWM
controller and are typically not changed during normal
operation of the PWM controller. Following a reset, all bits of
the PWMCFG register are cleared so that high frequency
chopping is disabled, by default.
Figure 60. Typical PWM Signals with High Frequency Gate Chopping Enabled
PWM Shut Down
In the event of external fault conditions, it is essential that the
PWM system be instantaneously shut down in a safe fashion. A
low level on the PWM
asynchronous (independent of the MicroConverter core clock)
shutdown of the PWM controller. All six PWM outputs are
placed in the off state, that is, high state. In addition, the
PWMSYNC pulse is disabled. The PWM
pull-down resistor to disable the PWM if the pin becomes
disconnected. The state of the PWM
Bit 3 of the PWMSTA register.
If a PWM shutdown command occurs, a PWMTRIP interrupt is
generated, and internal timing of the three-phase timing unit of
the PWM controller is stopped. Following a PWM shutdown, the
PWM can only be re-enabled (in a PWMTRIP interrupt service
routine, for example) by writing to all of the PWMDAT0,
PWMCH0, PWMCH1, and PWMCH2 registers. Provided that
the external fault is cleared and the PWMTRIP is returned to a
high level, the internal timing of the three-phase timing unit
resumes, and new duty-cycle values are latched on the next
PWMSYNC boundary.
Note that the PWMTRIP interrupt is available in IRQ only,
and the PWMSYNC interrupt is available in FIQ only. Both
interrupts share the same bit in the interrupt controller.
Therefore, only one of the interrupts can be used at once.
See the Interrupt System section for further details.
0H
0L
f
CHOP
2 × PWMDAT1
= f
CORE
PWMDAT0
4 × (GDCLK + 1) ×
on Both High-Side and Low-Side Switches
/(4 × (GDCLK + 1))
TRIP
PWMCH0
pin provides an instantaneous,
t
CORE
PWMCH0
TRIP
pin can be read from
TRIP
PWMDAT0
pin has an internal
2 × PWMDAT1