ADUC7025BCPZ32-RL7 AD [Analog Devices], ADUC7025BCPZ32-RL7 Datasheet - Page 67

• Manufacturer Part Number: ADUC7025BCPZ32-RL7
• Description: Precision Analog Microcontroller 12-bit Analog I/O, ARM7TDMI MCU
• Manufacturer: AD [Analog Devices]

ADuC7019/20/21/22/24/25/26/27
Table 59. SPICON MMR Bit Descriptions
Bit
15:13
12
11
10
9
8
7
6
5
4
3
2
1
0
I
The ADuC7019/7020/7021/7022/7024/7025/7026/7027 support
two fully licensed I
implemented as a full hardware master and slave interface. Because
the two I
I2C0 in detail. Note that the two masters and one of the slaves have
individual interrupts. See the Interrupt System section.
The two pins used for data transfer, SDA and SCL, are
configured in a wired-AND format that allows arbitration in a
multimaster system.
The I
programmed by the user. This ID can be modified any time a
transfer is not in progress. The user can configure the interface
to respond to four slave addresses.
The transfer sequence of an I
device initiating a transfer by generating a start condition while
the bus is idle. The master transmits the address of the slave
device and the direction of the data transfer in the initial
address transfer. If the master does not lose arbitration and the
slave acknowledges, then the data transfer is initiated. This
continues until the master issues a stop condition and the bus
becomes idle.
The I
independent and can be simultaneously active. A slave is
activated when a transfer has been initiated on the bus. If it is
not addressed, it remains inactive until another transfer is
initiated. This also allows a master device, which loses
arbitration, to respond as a slave in the same cycle.
2
C COMPATIBLE INTERFACES
2
2
C peripheral master and slave functionality are
C bus peripheral’s address in the I
2
C interfaces are identical, this data sheet describes only
Description
Reserved.
Continuous Transfer Enable. Set by user to enable continuous transfer. In master mode, the transfer continues until no valid data
is available in the TX register. CS is asserted and remains asserted for the duration of each 8-bit serial transfer until TX is empty.
Cleared by user to disable continuous transfer. Each transfer consists of a single 8-bit serial transfer. If valid data exists in the
SPITX register, then a new transfer is initiated after a stall period.
Loop Back Enable. Set by user to connect MISO to MOSI and test software. Cleared by user to be in normal mode.
Slave Output Enable. Set by user to enable the slave output. Cleared by user to disable slave output.
Slave Select Input Enable. Set by user in master mode to enable the output. Cleared by user to disable master output.
SPIRX Overflow Overwrite Enable. Set by user, the valid data in the RX register is overwritten by the new serial byte received.
Cleared by user, the new serial byte received is discarded.
SPITX Underflow Mode. Set by user to transmit 0. Cleared by user to transmit the previous data.
Transfer and Interrupt Mode. Set by user to initiate transfer with a write to the SPITX register. Interrupt only occurs when TX is
empty. Cleared by user to initiate transfer with a read of the SPIRX register. Interrupt only occurs when RX is full.
LSB First Transfer Enable Bit. Set by user, the LSB is transmitted first. Cleared by user, the MSB is transmitted first.
Reserved.
Serial Clock Polarity Mode Bit. Set by user, the serial clock idles high. Cleared by user, the serial clock idles low.
Serial Clock Phase Mode Bit. Set by user, the serial clock pulses at the beginning of each serial bit transfer. Cleared by user, the
serial clock pulses at the end of each serial bit transfer.
Master Mode Enable Bit. Set by user to enable master mode. Cleared by user to enable slave mode.
SPI Enable Bit. Set by user to enable the SPI. Cleared by user to disable the SPI.
2
C interfaces. The I
2
C system consists of a master
2
C interfaces are both
2
C bus system is
Rev. A | Page 67 of 92
Serial Clock Generation
The I
transfer. The master channel can be configured to operate in
fast mode (400 kHz) or standard mode (100 kHz).
The bit rate is defined in the I2C0DIV MMR as follows:
where:
f
DIVH = the high period of the clock.
DIVL = the low period of the clock.
Thus, for 100 kHz operation,
and for 400 kHz,
The I2C×DIV register corresponds to DIVH:DIVL.
Slave Addresses
The registers I2C0ID0, I2C0ID1, I2C0ID2, and I2C0ID3
contain the device IDs. The device compares the four I2C0IDx
registers to the address byte. The seven most significant bits of
either ID register must be identical to that of the seven most
significant bits of the first address byte received to be correctly
addressed. The LSB of the ID registers, the transfer direction
bit, is ignored in the process of address recognition.
UCLK
DIVH = DIVL = 0×CF
DIVH = DIVL = 0×32
= clock before the clock divider.
2
C master in the system generates the serial clock for a
f
serialcloc
k
=
2 (
+
DIVH
f
UCLK
)
+
(2
+
DIVL
)