ADUC7025BCPZ32-RL7 AD [Analog Devices], ADUC7025BCPZ32-RL7 Datasheet - Page 59

• Manufacturer Part Number: ADUC7025BCPZ32-RL7
• Description: Precision Analog Microcontroller 12-bit Analog I/O, ARM7TDMI MCU
• Manufacturer: AD [Analog Devices]

PWM MMRs Interface
The PWM block is controlled via the MMRs described in this
section.
PWMCON Register
Name
PWMCON
PWMCON is a control register that enables the PWM and
chooses the update rate.
Table 35. PWMCON MMR Bit Descriptions
Bit
7:5
4
3
2
1
0
PWMSTA Register
Name
PWMSTA
PWMSTA reflects the status of the PWM.
Table 36. PWMSTA MMR Bit Descriptions
Bit
15:10
9
8
3
2:1
0
Name
PWM_SYNCSEL
PWM_EXTSYNC
PWMDBL
PWM_SYNC_EN
PWMEN
Name
PWMSYNCINT
PWMTRIPINT
PWMTRIP
PWMPHASE
Address
0xFFFFFC00
Address
0xFFFFFC04
Description
Reserved.
External Sync Select. Set to use external
sync. Cleared to use internal sync.
External Sync Select. Set to select
external synchronous sync signal.
Cleared for asynchronous sync signal.
Double Update Mode. Set to 1 by user
to enable double update mode.
Cleared to 0 by the user to enable
single update mode.
PWM Synchronization Enable. Set by
user to enable synchronization. Cleared
by user to disable synchronization.
PWM Enable Bit. Set to 1 by the user
to enable the PWM. Cleared to 0 by
the user to disable the PWM. Also
cleared automatically with PWMTRIP.
Description
Reserved.
PWM Sync Interrupt Bit.
PWM Trip Interrupt Bit.
Raw Signal from the PWM
Reserved.
PWM Phase Bit. Set to 1 by the Micro-
Converter when the timer is counting
down (1
MicroConverter when the timer is
counting up (2
Default Value
0x0000
Default Value
0x0000
st
half). Cleared to 0 by the
nd
half).
TRIP
Access
R/W
Access
R/W
Pin.
Rev. A | Page 59 of 92
PWMCFG Register
Name
PWMCFG
PWMCFG is a gate chopping register.
Table 37. PWMCFG MMR Bit Descriptions
Bit
15:10
9
8
7:0
PWMEN Register
Name
PWMEN
PWMEN allows enabling channel outputs and crossover. See its
bit definitions in Table 38.
Table 38. PWMEN MMR Bit Descriptions
Bit
8
7
6
5
4
3
2
1
0
Name
0H0L_XOVR
1H1L_XOVR
2H2L_XOVR
0L_EN
0H_EN
1L_EN
1H_EN
2L_EN
2H_EN
ADuC7019/20/21/22/24/25/26/27
Name
CHOPLO
CHOPHI
GDCLK
Address
0xFFFFFC10
Address
0xFFFFFC20
Description
Channel 0 Output Crossover Enable Bit. Set
to 1 by user to enable Channel 0 output
crossover. Cleared to 0 by user to disable
Channel 0 output crossover.
Channel 1 Output Crossover Enable Bit. Set
to 1 by user to enable Channel 1 output
crossover. Cleared to 0 by user to disable
Channel 1 output crossover.
Channel 2 Output Crossover Enable Bit. Set
to 1 by user to enable Channel 2 output
crossover. Cleared to 0 by user to disable
Channel 2 output crossover.
0L Output Enable Bit. Set to 1 by user to
disable the 0L output of the PWM. Cleared
to 0 by user to enable the 0L output of the
PWM.
0H Output Enable Bit. Set to 1 by user to
disable the 0H output of the PWM. Cleared
to 0 by user to enable the 0H output of the
PWM.
1L Output Enable Bit. Set to 1 by user to
disable the 1L output of the PWM. Cleared
to 0 by user to enable the 1L output of the
PWM.
1H Output Enable Bit. Set to 1 by user to
disable the 1H output of the PWM. Cleared
to 0 by user to enable the 1H output of the
PWM.
2L Output Enable Bit. Set to 1 by user to
disable the 2L output of the PWM. Cleared
to 0 by user to enable the 2L output of the
PWM.
2H Output Enable Bit. Set to 1 by user to
disable the 2H output of the PWM. Cleared
to 0 by user to enable the 2H output of the
PWM.
Description
Reserved.
Low-side gate chopping enable bit.
High-side gate chopping enable bit.
PWM gate chopping period (unsigned).
Default Value
0x0000
Default Value
0x0000
Access
R/W
Access
R/W