ADUC7025BCPZ32-RL7 AD [Analog Devices], ADUC7025BCPZ32-RL7 Datasheet - Page 15

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ADUC7025BCPZ32-RL7

Manufacturer Part Number
ADUC7025BCPZ32-RL7
Description
Precision Analog Microcontroller 12-bit Analog I/O, ARM7TDMI MCU
Manufacturer
AD [Analog Devices]
Datasheet
Table 8. SPI Slave Mode Timing (PHASE Mode = 0)
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
1
2
CS
SL
SH
DAV
DSU
DHD
DF
DR
SR
SF
DOCS
SFS
t
t
UCLK
HCLK
= 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider.
depends on the clock divider or CD bits in PLLCON MMR. t
(POLARITY = 0)
(POLARITY = 1)
Description
CS to SCLOCK edge
SCLOCK low pulse width
SCLOCK high pulse width
Data output valid after SCLOCK edge
Data input setup time before SCLOCK edge
Data input hold time after SCLOCK edge
Data output fall time
Data output rise time
SCLOCK rise time
SCLOCK fall time
Data output valid after CS edge
CS high after SCLOCK edge
SCLOCK
SCLOCK
MISO
MOSI
CS
t
DOCS
t
CS
1
t
DSU
MSB IN
2
2
t
MSB
DHD
t
SH
Figure 9. SPI Slave Mode Timing (PHASE Mode = 0)
t
DF
HCLK
t
DAV
= t
1
UCLK
t
SL
Rev. A | Page 15 of 92
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1
t
CD
DR
.
BITS 6–1
BITS 6–1
Min
2 × t
2 × t
1 × t
2 × t
0
ADuC7019/20/21/22/24/25/26/27
HCLK
UCLK
UCLK
UCLK
LSB IN
t
SR
+
LSB
Typ
(SPIDIV + 1) × t
(SPIDIV + 1) × t
5
5
5
5
t
SF
t
SFS
HCLK
HCLK
Max
25
12.5
12.5
12.5
12.5
25
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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