ADUC7025BCPZ32-RL7 AD [Analog Devices], ADUC7025BCPZ32-RL7 Datasheet - Page 43

• Manufacturer Part Number: ADUC7025BCPZ32-RL7
• Description: Precision Analog Microcontroller 12-bit Analog I/O, ARM7TDMI MCU
• Manufacturer: AD [Analog Devices]

NONVOLATILE FLASH/EE MEMORY
The ADuC7019/7020/7021/7022/7024/7025/7026/7027
incorporate Flash/EE memory technology on-chip to provide
the user with nonvolatile, in-circuit reprogrammable memory
space.
Like EEPROM, flash memory can be programmed in-system at
a byte level, although it must first be erased. The erase is
performed in page blocks. As a result, flash memory is often
and more correctly referred to as Flash/EE memory.
Overall, Flash/EE memory represents a step closer to the ideal
memory device that includes nonvolatility, in-circuit
programmability, high density, and low cost. Incorporated in
the ADuC7019/7020/7021/7022/7024/7025/7026/7027,
Flash/EE memory technology allows the user to update
program code space in-circuit, without the need to replace one
time programmable (OTP) devices at remote operating nodes.
Each ADuC7019/7020/7021/7022/7024/7025/7026/7027
contains a 64 kB array of Flash/EE memory. The lower 62 kB is
available to the user and the upper 2 kB contain permanently
embedded firmware, allowing in-circuit serial download. These
2 kB of embedded firmware also contain a power-on
configuration routine that downloads factory calibrated
coefficients to the various calibrated peripherals (such as ADC,
temperature sensor, and band gap references). This 2 kB
embedded firmware is hidden from user code.
Flash/EE Memory Reliability
The Flash/EE memory arrays on the parts is fully qualified for
two key Flash/EE memory characteristics: Flash/EE memory
cycling endurance and Flash/EE memory data retention.
Endurance quantifies the ability of the Flash/EE memory to be
cycled through many program, read, and erase cycles. A single
endurance cycle is composed of four independent, sequential
events, defined as:
1. Initial page erase sequence.
2. Read/verify sequence a single Flash/EE.
3. Byte program sequence memory.
4. Second read/verify sequence endurance cycle.
In reliability qualification, every half word (16-bit wide)
location of the three pages (top, middle, and bottom) in the
Flash/EE memory is cycled 10,000 times from 0x0000 to
0xFFFF. As indicated in Table 1, the parts’ Flash/EE memory
endurance qualification is carried out in accordance with
JEDEC Retention Lifetime Specification A117 over the
industrial temperature range of -- - 40°C to +25°C and +25°C to
+125°C. The results allow the specification of a minimum
endurance figure over supply temperature of 10,000 cycles.
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Retention quantifies the ability of the Flash/EE memory to
retain its programmed data over time. Again, the parts is
qualified in accordance with the formal JEDEC Retention
Lifetime Specification (A117) at a specific junction temperature
(T
Flash/EE memory is cycled to its specified endurance limit,
described previously, before data retention is characterized.
This means that the Flash/EE memory is guaranteed to retain
its data for its fully specified retention lifetime every time the
Flash/EE memory is reprogrammed. Also note that retention
lifetime, based on an activation energy of 0.6 eV, derates with T
as shown in Figure 49.
PROGRAMMING
The 62 kB of Flash/EE memory can be programmed in-circuit,
using the serial download mode or the JTAG mode provided.
Serial Downloading (In-Circuit Programming)
The ADuC7019/7020/7021/7022/7024/7025/7026/7027
facilitate code download via the standard UART serial port or
via the I
reset or power cycle if the BM pin is pulled low through an
external 1 kΩ resistor. Once in serial download mode, the user
can download code to the full 62 kB of Flash/EE memory while
the device is in-circuit in its target application hardware. An
executable PC serial download is provided as part of the
development system for serial downloading via the UART. An
application note is available at www.analog.com/microconverter
describing the protocol for serial downloading via the UART
and I
JTAG Access
The JTAG protocol uses the on-chip JTAG interface to facilitate
code download and debug. An application note is available at
www.analog.com/microconverter describing the protocol via
JTAG.
J
= 85°C). As part of this qualification procedure, the
2
C.
600
450
300
150
2
0
C port. The parts enter serial download mode after a
ADuC7019/20/21/22/24/25/26/27
30
Figure 49. Flash/EE Memory Data Retention
40
JUNCTION TEMPERATURE (°C)
55
70
85
100
125
135
150
J