ADUC7025BCPZ32-RL7 AD [Analog Devices], ADUC7025BCPZ32-RL7 Datasheet - Page 78

• Manufacturer Part Number: ADUC7025BCPZ32-RL7
• Description: Precision Analog Microcontroller 12-bit Analog I/O, ARM7TDMI MCU
• Manufacturer: AD [Analog Devices]

ADuC7019/20/21/22/24/25/26/27
T2CON Register
Name
T2CON
T2CON is the configuration MMR described in Table 76.
Table 76. T2CON MMR Bit Descriptions
Bit
31:11
10:9
8
7
6
5:4
3:0
T2CLRI Register
Name
T2CLRI
T2CLRI is an 8-bit register. Writing any value to this register
clears the Timer2 interrupt.
Timer3 (Watchdog Time)
Timer3 has two modes of operation, normal mode and
watchdog mode. The watchdog timer is used to recover from
an illegal software state. Once enabled, it requires periodic
servicing to prevent it from forcing a reset of the processor.
Normal Mode
Timer3 in normal mode is identical to Timer0, except for the
clock source and the count-up functionality. The clock source is
32 kHz from the PLL and can be scaled by a factor of 1, 16, or
256 (see Figure 66).
Value
00
01
10
11
00
01
10
11
0000
0100
1000
1111
Address
0xFFFF0348
Address
0xFFFF034C
Description
Clock Source.
External Crystal.
External Crystal.
Internal Oscillator.
Reserved.
Hr:Min:Sec:Hundredths (23 hours to 0 hour).
Prescale:
Source Clock/1 by Default.
Source Clock/16.
Source Clock/256 Expected for Format 2 and 3.
Source Clock/32768.
Reserved.
Core Clock (41 MHz/2
Count Up. Set by user for Timer2 to count up.
Cleared by user for Timer2 to count down by
default.
Timer2 Enable Bit. Set by user to enable Timer2.
Cleared by user to disable Timer2 by default.
Timer2 Mode. Set by user to operate in
periodic mode. Cleared by user to operate in
free-running mode. Default mode.
Format.
Binary.
Hr:Min:Sec:Hundredths (255 hours to 0 hour).
Default Value
0x0000
Default Value
0xFF
CD
).
Access
R/W
Access
W
Rev. A | Page 78 of 92
Watchdog Mode
Watchdog mode is entered by setting Bit 5 in T3CON MMR.
Timer3 decreases from the value present in T3LD register until
zero. T3LD is used as timeout. The maximum timeout can be
512 seconds using the prescaler/256, and full-scale in T3LD.
Timer3 is clocked by the internal 32 kHz crystal when
operating in the watchdog mode. Note that to enter watchdog
mode successfully, Bit 5 in the T3CON MMR must be set after
writing to the T3LD MMR.
If the timer reaches 0, a reset or an interrupt occurs, depending
on Bit 1 in T3CON register. To avoid reset or interrupt, any value
must be written to T3ICLR before the expiration period. This
reloads the counter with T3LD and begins a new timeout period.
As soonas watchdog mode is entered, T3LD and T3CON are
write-protected. These two registers cannot be modified until a
reset clears the watchdog enable bit, which causes Timer3 to
exit watchdog mode.
The Timer3 interface consists of four MMRS: T3LD, T3VAL,
T3CON, and T3CLRI.
T3LD Register
Name
T3LD
T3LD is a 16-bit register load register.
T3VAL Register
Name
T3VAL
T3VAL is a 16-bit read-only register that represents the current
state of the counter.
T3CON Register
Name
T3CON
T3CON is the configuration MMR described in Table 77.
32.768kHz
Address
0xFFFF0360
Address
0xFFFF0364
Address
0xFFFF0368
Figure 66. Timer3 Block Diagram
PRESCALER
/1, 16 OR 256
Default Value
0x0000
Default Value
0xFFFF
Default Value
0x0000
COUNTER
UP/DOWN
TIMER3
VALUE
16-BIT
16-BIT
LOAD
WATCHDOG
RESET
TIMER3 IRQ
Access
R/W
Access
R
Access
R/W