ADUC7025BCPZ32-RL7 AD [Analog Devices], ADUC7025BCPZ32-RL7 Datasheet - Page 60

• Manufacturer Part Number: ADUC7025BCPZ32-RL7
• Description: Precision Analog Microcontroller 12-bit Analog I/O, ARM7TDMI MCU
• Manufacturer: AD [Analog Devices]

ADuC7019/20/21/22/24/25/26/27
PWMDAT0 Register
Name
PWMDAT0
PWMDAT0 is an unsigned 16-bit register for switching period.
PWMDAT1 Register
Name
PWMDAT1
PWMDAT1 is an unsigned 10-bit register for dead time.
PWMCHx Registers
Name
PWMCH0
PWMCH1
PWMCH2
PWMCH0, PWMCH1, and PWMCH2 are channel duty cycles
for the three phases.
PWMDAT2 Register
Name
PWMDAT2
PWMDAT2 is an unsigned 10-bit register for PWM sync pulse
width.
GENERAL-PURPOSE INPUT/OUTPUT
The ADuC7019/7020/7021/7022/7024/7025/7026/7027 provide
40 general-purpose, bi-directional I/O (GPIO) pins. All I/O pins
are 5 V tolerant, which means that the GPIOs support an input
voltage of 5 V. In general, many of the GPIO pins have multiple
functions (see Table 39 for the pin function definitions). By
default, the GPIO pins are configured in GPIO mode.
All GPIO pins have an internal pull-up resistor (of about 100 kΩ)
and their drive capability is 1.6 mA. Note that a maximum of
20 GPIO can drive 1.6 mA at the same time. The following GPIO
have programmable pull up: P0.0, P0.4, P0.5, P0.6, P0.7, and the
8 GPIOs of P1.
The 40 GPIO are grouped in five ports, Port 0 to Port 4. Each
port is controlled by four or five MMRs, x representing the port
number.
Note that the kernel changes P0.6 from its default configuration
at reset (MRST) to GPIO mode. If MRST is used for external
circuitry, an external pull-up resistor should be used to ensure
that the level on P0.6 does not drop when the kernel switches
mode. For example, if MRST is required for power down, it can
be reconfigured in GP0CON MMR.
The input level of any GPIO can be read at any time in the
GPxDAT MMR, even when the pin is configured in a different
mode than GPIO. The PLA input are also always active.
Address
0xFFFFFC08
Address
0xFFFFFC0C
Address
0xFFFFFC14
0xFFFFFC18
0xFFFFFC1C
Address
0xFFFFFC24
Default Value
0x0000
Default Value
0x0000
Default Value
0x0000
0x0000
0x0000
Default Value
0x0000
Access
R/W
Access
R/W
Access
R/W
R/W
R/W
Access
R/W
Rev. A | Page 60 of 92
Table 39. GPIO Pin Function Descriptions
Port
0
1
2
3
4
1
2
GPxCON Registers
Name
GP0CON
GP1CON
GP2CON
GP3CON
GP4CON
When configured in Mode 1, P0.7 is ECLK by default, or core clock output.
To configure it as a clock input, MDCLK bits in PLLCON must be set to 11.
The CONV
Pin
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
P4.0
P4.1
P4.2
P4.3
P4.4
P4.5
P4.6
P4.7
START
signal is active in all modes of P2.0.
00
GPIO
GPIO
GPIO
GPIO
GPIO/IRQ0
GPIO/IRQ1
GPIO/T1
GPIO
GPIO/T1
GPIO
GPIO
GPIO
GPIO/IRQ2
GPIO/IRQ3
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
Address
0xFFFFF400
0xFFFFF404
0xFFFFF408
0xFFFFF40C
0xFFFFF410
Configuration
01
CMP
PWM2
PWM2
TRST
PWM
ADC
MRST
ECLK/XCLK
SIN
SOUT
RTS
CTS
RI
DCD
DSR
DTR
CONV
PWM0
PWM0
PWM0
PWM0
PWM1
PWM1
PWM0
PWM0
PWM1
PWM1
PWM2
PWM2
PWM
PWM
Default Value
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
BUSY
TRIP
TRIP
SYNC
START
H
L
H
L
H
L
H
L
H
L
H
L
H
L
2
1
10
MS2
BLE
BHE
A16
MS1
MS0
AE
SIN
SCL0
SDA0
SCL1
SDA1
CLK
MISO
MOSI
CSL
SOUT
WS
RS
AE
MS0
MS1
MS2
MS3
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
Access
R/W
R/W
R/W
R/W
R/W
11
PLAI[7]
ADC
PLAO[1]
PLAO[2]
PLAO[3]
PLAO[4]
PLAI[0]
PLAI[1]
PLAI[2]
PLAI[3]
PLAI[4]
PLAI[5]
PLAI[6]
PLAO[0]
PLAO[5]
PLAO[6]
PLAO[7]
PLAI[8]
PLAI[9]
PLAI[10]
PLAI[11]
PLAI[12]
PLAI[13]
PLAI[14]
PLAI[15]
PLAO[8]
PLAO[9]
PLAO[10]
PLAO[11]
PLAO[12]
PLAO[13]
PLAO[14]
PLAO[15]
BUSY