ADUC7025BCPZ32-RL7 AD [Analog Devices], ADUC7025BCPZ32-RL7 Datasheet - Page 40

• Manufacturer Part Number: ADUC7025BCPZ32-RL7
• Description: Precision Analog Microcontroller 12-bit Analog I/O, ARM7TDMI MCU
• Manufacturer: AD [Analog Devices]

ADuC7019/20/21/22/24/25/26/27
ADCCN Register
Name
ADCCN
ADCCN is an ADC negative channel selection register. This
MMR is described in Table 16.
Table 16. ADCCN MMR Bit Designation
Bit
7:5
4:0
ADCSTA Register
Name
ADCSTA
ADCSTA is an ADC status register that indicates when an ADC
conversion result is ready. The ADCSTA register contains only
one bit, ADCReady (Bit 0), representing the status of the ADC.
This bit is set at the end of an ADC conversion, generating an
ADC interrupt. It is cleared automatically by reading the
ADCDAT MMR. When the ADC is performing a conversion,
the status of the ADC can be read externally via the ADC
pin. This pin is high during a conversion. When the conversion
is finished, ADC
available on P0.5 (see the General-Purpose Input/Output
section) if enabled in the ADCCON register.
ADCDAT Register
Name
ADCDAT
ADCDAT is an ADC data result register. Hold the 12-bit ADC
result as shown in Figure 39.
ADCRST Register
Name
ADCRST
Value
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
Others
Address
0xFFFF0508
Address
0xFFFF050C
Address
0xFFFF0510
Address
0xFFFF0514
BUSY
Description
Reserved
Negative channel selection bits
ADC0
ADC1
ADC2
ADC3
ADC4
ADC5
ADC6
ADC7
ADC8
ADC9
ADC10
ADC11
DAC0/ADC12
DAC1/ADC13
DAC2/ADC14
DAC3/ADC15
Internal reference (self-diagnostic feature)
Reserved
goes back low. This information can be
Default Value
0x01
Default Value
0x00
Default Value
0x00000000
Default Value
0x00
Access
R/W
Access
R
Access
R
Access
R/W
BUSY
Rev. A | Page 40 of 92
ADCRST resets the digital interface of the ADC. Writing any
value to this register resets all the ADC registers to their default
value.
ADCGN Register
Name
ADCGN
ADCGN is a 10-bit gain calibration register.
ADCOF Register
Name
ADCOF
ADCOF is a 10-bit offset calibration register.
CONVERTER OPERATION
The ADC incorporates a successive approximation (SAR)
architecture involving a charge-sampled input stage. This
architecture can operate in three different modes: differential,
pseudo differential, and single-ended.
Differential Mode
The ADuC7019/7020/7021/7022/7024/7025/7026/7027 each
contain a successive approximation ADC based on two
capacitive DACs. Figure 42 and Figure 43 show simplified
schematics of the ADC in acquisition and conversion phase,
respectively. The ADC is comprised of control logic, a SAR, and
two capacitive DACs. In Figure 42 (the acquisition phase), SW3
is closed and SW1 and SW2 are in Position A. The comparator
is held in a balanced condition, and the sampling capacitor
arrays acquire the differential signal on the input.
AIN11
When the ADC starts a conversion, as shown in Figure 43, SW3
opens, and then SW1 and SW2 move to Position B. This causes
the comparator to become unbalanced. Both inputs are discon-
nected once the conversion begins. The control logic and the
charge redistribution DACs are used to add and subtract fixed
amounts of charge from the sampling capacitor arrays to bring
the comparator back into a balanced condition. When the
comparator is rebalanced, the conversion is complete. The
control logic generates the ADC’s output code. The output
impedances of the sources driving the V
be matched; otherwise, the two inputs have different settling
times, resulting in errors.
AIN0
MUX
CHANNEL+
CHANNEL–
Address
0xFFFF0530
Address
0xFFFF0534
Figure 42. ADC Acquisition Phase
B
A
A
B
V
REF
SW1
SW2
C
C
S
S
Default Value
0x0200
Default Value
0x0200
SW3
COMPARATOR
IN+
and V
IN–
CAPACITIVE
CAPACITIVE
pins must
CONTROL
DAC
LOGIC
DAC
Access
R/W
Access
R/W