ADUC7025BCPZ32-RL7 AD [Analog Devices], ADUC7025BCPZ32-RL7 Datasheet - Page 72

• Manufacturer Part Number: ADUC7025BCPZ32-RL7
• Description: Precision Analog Microcontroller 12-bit Analog I/O, ARM7TDMI MCU
• Manufacturer: AD [Analog Devices]

ADuC7019/20/21/22/24/25/26/27
PLAELMx are Element 0 to Element 15 control registers. They
configure the input and output mux of each element, select the
function in the look-up table, and bypass/use the flip-flop. See
Table 65 and Table 67.
Table 65. PLAELMx MMR Bit Descriptions
Bit
31:11
10:9
8:7
6
5
4:1
0
Table 67. Feedback Configuration
Bit
10:9
8:7
Value
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Value
00
01
10
11
00
01
10
11
Reserved.
Look-Up Table Control.
Description
Mux (0) Control (see Table 67).
Mux (1) Control (see Table 67).
Mux (2) Control. Set by user to select the
output of mux (0). Cleared by user to select
the bit value from PLADIN.
Mux (3) Control. Set by user to select the
input pin of the particular element. Cleared
by user to select the output of mux (1).
0.
NOR.
B AND NOT A.
NOT A.
A AND NOT B.
NOT B.
EXOR.
NAND.
AND.
EXNOR.
B.
NOT A OR B.
A.
A OR NOT B.
OR.
1.
Mux (4) Control. Set by user to bypass the flip-
flop. Cleared by user to select the flip-flop
(cleared by default).
PLAELM0
Element 15
Element 2
Element 4
Element 6
Element 1
Element 3
Element 5
Element 7
Rev. A | Page 72 of 92
PLAELM1 to PLAELM7
Element 0
Element 2
Element 4
Element 6
Element 1
Element 3
Element 5
Element 7
PLACLK Register
Name
PLACLK
PLACLK is a clock selection for the flip-flops of Block 0 and
clock selection for the flip-flops of Block 1.
Table 66. PLACLK MMR Bit Descriptions
Bit
7
6:4
3
2:0
Value
000
001
010
011
100
101
Other
000
001
010
011
100
101
Other
PLAELM8
Element 7
Element 10
Element 12
Element 14
Element 9
Element 11
Element 13
Element 15
Address
0xFFFF0B40
Description
Reserved
Block 1 Clock Source Selection
GPIO Clock on P0.5
GPIO Clock on P0.0
GPIO Clock on P0.7
HCLK
OCLK (32.768 kHz)
Timer1 Overflow
Reserved
Reserved
Block 0 Clock Source Selection
GPIO Clock on P0.5
GPIO Clock on P0.0
GPIO Clock on P0.7
HCLK
OCLK (32.768 kHz)
Timer1 Overflow
Reserved
Default Value
0x00
PLAELM9 to PLAELM15
Element 8
Element 10
Element 12
Element 14
Element 9
Element 11
Element 13
Element 15
Access
R/W