HD6435348R Hitachi Semiconductor, HD6435348R Datasheet - Page 113

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HD6435348R

Manufacturer Part Number
HD6435348R
Description
Single-Chip Microcomputer
Manufacturer
Hitachi Semiconductor
Datasheet
(Example)
ADD.W R2,R0
MOV.W R0,@H'FE00
MOV.W #H'FE02,R0
4.9 Stack Status after Completion of Exception Handling
The status of the stack after an exception-handling sequence is described below.
Table 4-3 shows the stack after completion of the exception-handling sequence for various types
of exceptions in the minimum and maximum modes.
Table 4-3 Stack after Exception Handling Sequence
Exception Factor
Trace
Interrupt
Trap
Zero divide
(DIVXU)
Note: The RTE instruction returns to the next instruction after the instruction being executed when
.
.
.
.
.
.
.
.
the exception occurred.
SP
Next instruction address (upper byte)
Next instruction address (lower byte)
Minimum Mode
SR (upper byte)
SR (lower byte)
Program flow
DTC interrupt request
After data transfer cycle, CPU
executes next instruction before
branching to exception handling
93
Data transfer cycle
Table 4-3
TP:SP
To NMI exception-handling sequence
Next instruction address (upper byte)
Next instruction address (lower byte)
Next instruction page (8 bits)
Maximum Mode
SR (upper byte)
SR (lower byte)
NMI interrupt
Don’t-care

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