HD6435348R Hitachi Semiconductor, HD6435348R Datasheet - Page 414

• Manufacturer Part Number: HD6435348R
• Description: Single-Chip Microcomputer
• Manufacturer: Hitachi Semiconductor

* Only writing of a 0 to
TCSR—Timer Control/Status Register
Bit
Initial value
Read/Write
clear the flag is enabled.
R/(W)*
ICF
7
0
R/(W)*
OCFB
Input Capture Flag
6
0
0
1
0
1
Cleared from 1 to 0 when:
1. CPU reads OCFB = 1, then writes 0 in OCFB.
2. OCIB interrupt is served by DTC.
Set to 1 when FRC = OCRB.
Cleared from 1 to 0 when:
1. CPU reads ICF = 1, then writes 0 in ICF.
2. ICI interrupt is served by DTC.
Set to 1 when input capture signal is received and FRC count is copied to ICR.
R/(W)*
OCFA
0
1
Output Compare Flag B
5
0
Cleared from 1 to 0 when:
1. CPU reads OCFA = 1, then writes 0 in OCFA.
2. OCIA interrupt is served by DTC.
Set to 1 when FRC = OCRA.
R/(W)*
Output Compare Flag A
404
0
1
OVF
4
0
Cleared from 1 to 0 when CPU reads OVF =
1, then writes 0 in OVF.
Set to 1 when FRC changes from H'FFFF to H'0000.
0
1
H'FE91
OLVLB
Timer Overflow
R/W
Compare-match B causes 0 output.
Compare-match B causes 1 output.
3
0
0
1
Output Level B
OLVLA
Compare-match A causes 0 output.
Compare-match A causes 1 output.
R/W
2
0
Input Edge Select
Output Level A
0
1
Count is captured on
falling edge of input
capture signal (FTI).
Count is captured on
rising edge of input
capture signal.
IEDG
R/W
1
0
Counter Clear A
0
1
CCLRA
FRC count
is not cleared.
FRC count is
cleared by
compare-
match A.
R/W
FRT1
0
0