HD6435348R Hitachi Semiconductor, HD6435348R Datasheet - Page 13

• Manufacturer Part Number: HD6435348R
• Description: Single-Chip Microcomputer
• Manufacturer: Hitachi Semiconductor

Figures
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3-10 (a) External Access Cycle (Read Access) ·············································································68
3-10 (b) External Access Cycle (Write Access) ············································································69
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5-3 (a) Stack before and after Interrupt Exception-Handling (Minimum Mode) ······················108
5-3 (b) Stack before and after Interrupt Exception-Handling (Maximum Mode) ·····················109
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6-1
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Block Diagram ···················································································································5
Pin Arrangement (CP-84, Top View) ················································································6
Pin Arrangement (CG-84, Top View) ················································································7
Pin Arrangement (FP-80A, TFP-80C, Top View) ·····························································8
H8/534 Memory Map in Each Operating Mode ······························································28
H8/536 Memory Map in Each Operating Mode ······························································29
CPU Operating Modes ·····································································································32
Registers in the CPU ········································································································33
Stack Pointer ····················································································································34
Combinations of Page Registers with Other Registers ····················································38
Short Absolute Addressing Mode and Base Register ······················································39
On-Chip Memory Access Timing ····················································································64
Pin States during Access to On-Chip Memory ································································65
Register Field Access Timing ··························································································66
Pin States during Register Field Access ··········································································67
Operating States ···············································································································70
State Transitions ··············································································································71
Bus-Right Release Cycle (During On-chip Memory Access Cycle) ·······························73
Bus-Right Release Cycle (During External Access Cycle) ·············································74
Bus-Right Release Cycle (During Internal CPU Operation) ···········································75
Types of Factors Causing Exception Handling ·······························································81
Reset Vector ·····················································································································84
Reset Sequence (Minimum Mode, On-Chip Memory) ···················································85
Reset Sequence (Maximum Mode, External Memory) ···················································86
Interrupt Sources (and Number of Interrupt Types) ························································90
Interrupt Controller Block Diagram ················································································98
Interrupt Handling Flowchart ························································································107
Interrupt Sequence (Minimum Mode, On-Chip Memory) ············································110
Interrupt Sequence (Maximum Mode, External Memory) ············································111
Block Diagram of Data Transfer Controller ··································································114
Flowchart of Data Transfer Cycle ··················································································119
DTC Vector Table ··········································································································120
DTC Vector Table Entry ································································································121
Order of Register Information ·······················································································122
Use of DTC to Receive Data via Serial Communication Interface 1 ····························126
Block Diagram of Wait-State Controller ·······································································128