HD6435348R Hitachi Semiconductor, HD6435348R Datasheet - Page 483

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HD6435348R

Manufacturer Part Number
HD6435348R
Description
Single-Chip Microcomputer
Manufacturer
Hitachi Semiconductor
Datasheet
Pins A
Low state of the RES pin is sampled. Pins A
High.
The clock output pins P1
RES pin is sampled. Both pins are initialized to the output state.
7
*
P1 / ø*
RES
Internal reset signal
A to A
P6 /A
P5 /A
R/W
AS, RD and DS (read)
WR and DS (write)
D to D (write)
I/O ports
to A
7
7
The dotted line indicates that P1 /ø is an input port if the corresponding DDR bit is 0,
but a clock output pin if the DDR bit is 1.
0
3
7
0
19
15
0
0
of the address bus and the R/W signal are initialized 1.5 ø clock periods after the
to P6 /A
to P5 /A
0
0
16
8
Figure E-4 Reset during Memory Access (Mode 4)
and
0
/ø and P1
0
1
/E are initialized 0.5 ø clock periods after the Low state of the
T
1
7
to A
473
0
T
2
are made Low. The R/W signal is made
T
3
T
1
High impedance
High impedance
High impedance
H’00

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