HD6435348R Hitachi Semiconductor, HD6435348R Datasheet - Page 234

• Manufacturer Part Number: HD6435348R
• Description: Single-Chip Microcomputer
• Manufacturer: Hitachi Semiconductor

Bits 2, 1, and 0—Clock Select (CKS2, CKS1, and CKS0): These bits select the internal or
external clock source for the timer counter. For the external clock source they select whether to
increment the count on the rising or falling edge of the clock input, or on both edges.
Bit 2
CKS2
0
0
0
0
1
1
1
1
11.2.4 Timer Control/Status Register (TCSR)—H'FED1
Bit
Initial value
Read/Write
The TCSR is an 8-bit readable and partially writable* register that indicates compare-match and
overflow status and selects the effect of compare-match events on the timer output signal (TMO).
The TCSR is initialized to H'10 at a reset and in the standby modes.
* Software can write a 0 in bits 7 to 5 to clear the flags, but cannot write a 1 in these bits.
Bit 7—Compare-Match Flag B (CMFB): This status flag is set to 1 when the timer count
matches the time constant set in TCORB.
Bit 1
CKS1
0
0
1
1
0
0
1
1
R/(W)*
CMFB
7
0
Bit 0
CKS0
0
1
0
1
0
1
0
1
R/(W)*
CMFA
6
0
Description
No clock source (timer stopped).
Internal clock source (ø/8).
Internal clock source (ø/64).
Internal clock source (ø/1024).
No clock source (timer stopped).
External clock source, counted on the rising edge.
External clock source, counted on the falling edge.
External clock source, counted on both the rising
and falling edges.
R/(W)*
OVF
5
0
218
—
—
4
1
OS3
R/W
3
0
OS2
R/W
2
0
(Initial value)
OS1
R/W
1
0
OS0
R/W
0
0