HD6435348R Hitachi Semiconductor, HD6435348R Datasheet - Page 15

• Manufacturer Part Number: HD6435348R
• Description: Single-Chip Microcomputer
• Manufacturer: Hitachi Semiconductor

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17-2 (a) Socket Adapter Pin Arrangements (H8/534) ·································································306
Setting of Overflow Flag (OVF) ····················································································201
Square-Wave Output (Example) ····················································································206
FRC Write-Clear Contention ·························································································207
FRC Write-Increment Contention ·················································································208
Contention between OCR Write and Compare-Match ··················································209
Block Diagram of 8-Bit Timer ·······················································································214
Count Timing for External Clock Input ·········································································221
Setting of Compare-Match Flags ···················································································222
Timing of Timer Output ·································································································222
Timing of Compare-Match Clear ··················································································223
Timing of External Reset ·······························································································223
Setting of Overflow Flag (OVF) ····················································································224
Example of Pulse Output ·······························································································225
TCNT Write-Clear Contention ······················································································226
TCNT Write-Increment Contention ···············································································227
Contention between TCOR Write and Compare-Match ················································228
Block Diagram of PWM Timer ·····················································································234
PWM Timing ·················································································································239
Block Diagram of Timer Counter ··················································································242
Writing to TCNT and TCSR ··························································································247
Writing to RSTCSR ·······································································································247
Operation in Watchdog Timer Mode ·············································································249
Operation in Interval Timer Mode ·················································································249
Setting of OVF Bit ·········································································································250
Setting of WRST Bit and Internal Reset Signal ····························································251
TCNT Write-Increment Contention ···············································································252
Reset Circuit (Example) ································································································253
Block Diagram of Serial Communication Interface ······················································256
Data Format in Asynchronous Mode ·············································································271
Phase Relationship between Clock Output and Transmit Data ·····································272
Data Format in Synchronous Mode ···············································································276
Sampling Timing (Asynchronous Mode) ······································································282
Block Diagram of A/D Converter ··················································································284
Read Access to A/D Data Register (When Register Contains H'AA40) ·······················290
A/D Operation in Single Mode (When Channel 1 is Selected) ·····································293
A/D Operation in Scan Mode (When Channels 0 to 2 are Selected) ·····························295
A/D Conversion Timing ································································································296
Timing of Setting of ADST Bit ·····················································································297
Block Diagram of On-Chip RAM ·················································································299
Block Diagram of On-Chip ROM ·················································································304