HD6435348R Hitachi Semiconductor, HD6435348R Datasheet - Page 264

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HD6435348R

Manufacturer Part Number
HD6435348R
Description
Single-Chip Microcomputer
Manufacturer
Hitachi Semiconductor
Datasheet
13.3.2 Interval Timer Mode
Interval timer operation begins when the WT/IT bit is cleared to 0 and the TME bit is set to 1.
In the interval timer mode, an interval timer interrupt request is generated each time the timer
count overflows. This function can be used to generate interrupts at regular intervals.
See figure 13-5.
H'FF
TCNT count
H'00
* The reset signals are output for 132 ø clock periods. The internal reset signal remains valid for 520 ø clock periods.
Internal reset signal
External reset signal
(RES)
H'FF
TCNT count
H'00
* Interval timer interrupt request
WT/IT = 0
TME = 1
Start
Figure 13-4 Operation in Watchdog Timer Mode
Figure 13-5 Operation in Interval Timer Mode
H'00 written
to TCNT
*
*
OVF = 1
Watchdog timer overflow
249
Reset
*
*
Start
*
H'00 written
to TCNT
*
Time t

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