HD6435348R Hitachi Semiconductor, HD6435348R Datasheet - Page 143

• Manufacturer Part Number: HD6435348R
• Description: Single-Chip Microcomputer
• Manufacturer: Hitachi Semiconductor

Table 6-6 Number of States before Interrupt Service
No. Reason for Wait
1
2
3
m: Number of wait states inserted in external memory access
6.4 Procedure for Using the DTC
A program that uses the DTC to transfer data must do the following:
1. Set the appropriate DTMR, DTSR, DTDR, and DTCR register information in the memory
2. Set the data transfer enable bit of the pertinent interrupt to 1, and set the priority of the interrupt
3. Set the interrupt enable bit in the control register for the interrupt source (or set the IRQ enable
Following these preparations, the DTC will be started each time the interrupt occurs. When the
number of bytes or words designated by the DTCR value have been transferred, after transferring
the last byte or word, the DTC generates a CPU interrupt.
The user-coded interrupt-handling routine must take action to prepare for or disable further DTC
data transfer: by readjusting the data transfer count, for example, or clearing the interrupt enable
bit. If no action is taken, the next interrupt of the same type will start the DTC with an initial data
transfer count of 65,536.
location indicated in the DTC vector table.
source (in the interrupt priority register) and the interrupt mask level (in the CPU status
register) so that the interrupt can be accepted.
bit).
Interrupt priority decision and comparison with
mask level in CPU status register
Maximum number of
states to completion
of current instruction
Saving of PC and SR
or PC, CP, and SR
and instruction prefetch Stack is in external memory 28 + 6m
Instruction is in on-chip
memory
Instruction is in external
memory
Stack is in on-chip RAM
124
Minimum Mode
2 states
38
(LDM instruction specifying all registers)
74 + 16m
(LDM instruction specifying all registers)
16
Number of States
Maximum Mode
21
41 + 10m