HD6435348R Hitachi Semiconductor, HD6435348R Datasheet - Page 211

• Manufacturer Part Number: HD6435348R
• Description: Single-Chip Microcomputer
• Manufacturer: Hitachi Semiconductor

10.3 CPU Interface
The FRC, OCRA, OCRB, and ICR are 16-bit registers, but they are connected to an 8-bit data
bus. When the CPU accesses these four registers, to ensure that both bytes are written or read
simultaneously, the access is performed using an 8-bit temporary register (TEMP).
These registers are written and read as follows.
• Register Write
• Register Read
Programs that access these four registers should normally use word access. Equivalently, they
may access first the upper byte, then the lower byte. Data will not be transferred correctly if the
bytes are accessed in reverse order, or if only one byte is accessed.
Coding Examples : Write the contents of R0 into OCRA in FRT1
The same considerations apply to access by the DTC.
Figure 10-2 shows the data flow when the FRC is accessed. The other registers are accessed in
the same way, except that when OCRA or OCRB is read, the upper and lower bytes are both
transferred directly to the CPU without using the temporary register.
When the CPU writes to the upper byte, the upper byte of write data is placed in TEMP. Next,
when the CPU writes to the lower byte, this byte of data is combined with the byte in TEMP
and all 16 bits are written in the register simultaneously.
When the CPU reads the upper byte, the upper byte of data is sent to the CPU and the lower
byte is placed in TEMP. When the CPU reads the lower byte, it receives the value in TEMP.
: Read ICR of FRT2
MOV.W R0, @H'FE94
MOV.W, @H'FEA8, R0
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