HD6435348R Hitachi Semiconductor, HD6435348R Datasheet - Page 92

• Manufacturer Part Number: HD6435348R
• Description: Single-Chip Microcomputer
• Manufacturer: Hitachi Semiconductor

In the hardware exception-handling sequence the CPU does the following:
1. Saves the program counter and status register (in minimum mode) or program counter, code
2. Clears the T bit in the status register to 0.
3. Fetches the start address of the exception-handling routine from the exception vector table.
4. Branches to that address, returning to the program execution state.
See section 4, “Exception Handling,” for further information on the exception-handling state.
3.8.4 Bus-Released State
When so requested, the CPU can grant control of the external bus to an external device. While an
external device has the bus right, the CPU is said to be in the bus-released state. The bus right is
controlled by two pins:
• BREQ:
• BACK:
The procedure by which the CPU enters and leaves the bus-released state is:
1. The CPU receives a Low BREQ signal from an external device.
2. The CPU places the address bus pins (A
3. The external device that requested the bus (with the BREQ signal) becomes the bus master. It
4. When the external device finishes using the bus, it clears the BREQ signal to the High level.
Bus Release Timing: The CPU can release the bus right at the following times:
The CPU does not recognize interrupts while the bus is released.
page register, and status register (in maximum mode) to the stack.
(RD, WR, R/W, DS, and AS) in the high-impedance state, sets the BACK pin to the Low level
to indicate that it has released the bus, then halts.
can use the data bus and address bus. The external device is responsible for manipulating the
bus control signals (RD, WR, R/W, DS, and AS).
The CPU then reassumes control of the bus and returns to the program execution state.
1. The BREQ signal is sampled during every memory access cycle (instruction prefetch or data
2. During execution of the MULXU and DIVXU instructions, since considerable time may
3. The bus right can also be released in the sleep mode.
read/write). If BREQ is Low, the CPU releases the bus right at the end of the cycle. (In
word data access to external memory or an address from H'FE80 to H'FFFF, the CPU does
not release the bus right until it has accessed both the upper and lower data bytes.)
pass without an instruction prefetch or data read/write, BREQ is also sampled at internal
machine cycles, and the bus right is released if BREQ is Low.
Input pin for the Bus Request signal from an external device
Output pin for the Bus Request Acknowledge signal from the CPU, indicating that
the CPU has released the bus
19
– A
72
0
), data bus pins (D
7
– D
0
) and bus control pins