HD6435348R Hitachi Semiconductor, HD6435348R Datasheet - Page 125

• Manufacturer Part Number: HD6435348R
• Description: Single-Chip Microcomputer
• Manufacturer: Hitachi Semiconductor

If the data transfer enable bit is cleared to 0 (or is nonexistent), the sequence proceeds as follows.
For the case in which the data transfer controller is started, see section 6, “Data Transfer
Controller.”
5. After the CPU has finished executing the current instruction, the program counter and status
6. The T (Trace) bit of the status register is cleared to 0, and the priority level of the interrupt is
7. The interrupt controller generates the vector address of the interrupt, and the entry at this
In step 7, the same difference between the minimum and maximum modes exists as in the reset
handling sequence. In the minimum mode, one word is copied from the vector table to the
program counter, then the interrupt-handling routine starts executing from the address indicated in
the program counter. In the maximum mode, two words are read. The lower byte of the first
word is copied to the code page register. The second word is copied to the program counter. The
interrupt-handling routine starts executing from the address indicated in the code page register and
program counter.
register (in minimum mode) or program counter, code page register, and status register (in
maximum mode) are saved to the stack, leaving the stack in the condition shown in figure 5-3
(a) or (b). The program counter value saved on the stack is the address of the next instruction
to be executed.
copied to bits I2 to I0, thus masking further interrupts unless they have a higher priority level.
When an NMI is accepted, the interrupt mask level in bits I2 to I0 is set to 7.
address in the exception vector table is read to obtain the starting address of the user-coded
interrupt handling routine.
106