HD6435348R Hitachi Semiconductor, HD6435348R Datasheet - Page 233
HD6435348R
Manufacturer Part Number
HD6435348R
Description
Single-Chip Microcomputer
Manufacturer
Hitachi Semiconductor
Datasheet
1.HD6435348R.pdf
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Bit 7—Compare-Match Interrupt Enable B (CMIEB): This bit selects whether to request
compare-match interrupt B (CMIB) when compare-match flag B (CMFB) in the timer
status/control register (TCSR) is set to 1.
Bit 7
CMIEB
0
1
Bit 6—Compare-Match Interrupt Enable A (CMIEA): This bit selects whether to request
compare-match interrupt A (CMIA) when compare-match flag A (CMFA) in the timer
status/control register (TCSR) is set to 1.
Bit 6
CMIEA
0
1
Bit 5—Timer Overflow Interrupt Enable (OVIE): This bit selects whether to request a timer
overflow interrupt (OVI) when the overflow flag (OVF) in the timer status/control register
(TCSR) is set to 1.
Bit 5
OVIE
0
1
Bits 4 and 3—Counter Clear 1 and 0 (CCLR1 and CCLR0): These bits select how the timer
counter is cleared: by compare-match A or B or by an external reset input.
Bit 4
CCLR1
0
0
1
1
Compare-match interrupt request B (CMIB) is disabled.
Compare-match interrupt request B (CMIB) is enabled.
Compare-match interrupt request A (CMIA) is disabled.
Compare-match interrupt request A (CMIA) is enabled.
Description
The timer overflow interrupt request (OVI) is disabled.
The timer overflow interrupt request (OVI) is enabled.
Bit 3
0
1
0
1
Description
Description
CCLR0
Not cleared.
Cleared on compare-match A.
Cleared on compare-match B.
Cleared on rising edge of external reset input signal.
Description
217
(Initial value)
(Initial value)
(Initial value)
(Initial value)
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