HD6435348R Hitachi Semiconductor, HD6435348R Datasheet - Page 119

• Manufacturer Part Number: HD6435348R
• Description: Single-Chip Microcomputer
• Manufacturer: Hitachi Semiconductor

then clears the NMI request, so if another interrupt is requested at the NMI pin during the NMI
exception-handling sequence, the NMI exception-handling sequence will be carried out again.
Coding Examples:
To select the rising edge of the NMI input:
To select the falling edge of the NMI input:
IRQ0 (Interrupt Request 0): An IRQ
pin. A Low IRQ
SYSCR1 is set to 1. IRQ
request will be ignored.
The IRQ
value in the upper four bits of IPRA. If bit 4 of data transfer enable register A (DTEA) is set to 1,
an IRQ
In the CPU interrupt-handling sequence for IRQ
and the interrupt mask level is set to the value in the upper four bits of IPRA.
Coding Examples:
To enable IRQ
To assign priority level 7 to IRQ
To have IRQ
IRQ
Low transition at the IRQ
request enable 1 bit (IRQ
IRQ
Interrupts IRQ
corresponding value in IPRA and IPRB. The lower four bits of IPRA determine the priority of
IRQ
of IPRB determine the priority of IRQ
interrupt controller and cleared during the corresponding interrupt exception-handling sequence.
Contention among IRQ
interrupt with the highest priority first and holding lower-priority interrupts pending. (Contention
between IRQ
table 5-2.)
5
1
1
E in SYSCR2. (see section 9.7, “Port 6.”)
. The upper four bits of IPRB determine the priority of IRQ
to IRQ
0
0
interrupt starts the data transfer controller. Otherwise the interrupt is served by the CPU.
interrupt can be assigned any priority level from 7 to 0 by setting the corresponding
0
2
5
start the DTC:
0
1
and IRQ
(Interrupt Request 1 to 5): An IRQ
to be requested by IRQ
to IRQ
0
input requests an IRQ
5
1
3
, or between IRQ
can be assigned any priority level from 7 (high) to 0 (low) by setting the
to IRQ
1
0
1
E) in SYSCR1 is set to 1. IRQ
must be held Low until the CPU accepts the interrupt. Otherwise the
to IRQ
5
0
:
is resolved when the CPU accepts the interrupt by taking the
5
pin. The IRQ
4
0
0
and IRQ
0
interrupt can be requested by a Low input to the IRQ
input:
4
interrupt if the interrupt request enable 0 bit (IRQ
and IRQ
100
0
5
, the T bit of the status register is cleared to 0,
. Interrupt requests IRQ
1
interrupt is enabled only when the interrupt
5
, is resolved by the priority order shown in
1
to IRQ
2
to IRQ
BSET.B #4, @H'FEFC
BCLR.B #4, @H'FEFC
BSET.B #5, @H'FEFC
OR.B
BSET.B #4, @H'FF08
5
interrupt is requested by a High-to-
2
5
and IRQ
are controlled by bits IRQ
#70, @H'FF00
1
to IRQ
3
. The lower four bits
5
are held in the
0
E) in
2
0
E to