HD6435348R Hitachi Semiconductor, HD6435348R Datasheet - Page 310
HD6435348R
Manufacturer Part Number
HD6435348R
Description
Single-Chip Microcomputer
Manufacturer
Hitachi Semiconductor
Datasheet
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15.4.3 Input Sampling Time and A/D Conversion Time
The A/D converter includes a built-in sample-and-hold circuit. Sampling of the input starts at a
time t
conversion begins after sampling is completed. Figure 15-5 shows the timing of these steps, and
table 15-4 lists the total conversion times (t
The total conversion time includes t
write time with the A/D conversion process, so the length of t
time therefore varies within the minimum to maximum ranges indicated in table 15-4.
In the scan mode, the ranges given in table 15-4 apply to the first conversion. The length of the
second and subsequent conversion processes is fixed at 256 states (when CKS = 0) or 128 states
(when CKS = 1).
D
after the ADST bit is set to 1. The sampling process lasts for a time t
ø
Internal address
bus
Write signal
Input sampling
timing
ADF
(1)
(2)
t
t
t
D
SPL
CONV
: ADCSR write cycle
: ADCSR address
: Synchronization delay
: Input sampling time
: Total A/D conversion time
(1)
(2)
t
D
Figure 15-5 A/D Conversion Timing
D
and t
t
SPL
SPL
CONV
. The purpose of t
296
) for the single mode.
t
CONV
D
is variable. The total conversion
D
is to synchronize the ADCSR
SPL
. The actual A/D
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