HD6435348R Hitachi Semiconductor, HD6435348R Datasheet - Page 481

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HD6435348R

Manufacturer Part Number
HD6435348R
Description
Single-Chip Microcomputer
Manufacturer
Hitachi Semiconductor
Datasheet
3. Mode 3
Figure E-4 shows how the pin states change when the RES pin goes Low during external memory
access in mode 3.
As soon as RES goes Low, all ports are initialized to the input (high-impedance) state. The AS,
DS, RD, and WR signals all go High. The data bus (D
to D
) is placed in the high-impedance
7
0
state.
The address bus and the R/W signal are initialized 1.5 ø clock periods after the Low state of the
RES pin is sampled. All address bus signals are made Low. The R/W signal is made High.
The clock output pins P1
/ø and P1
/E are initialized 0.5 ø clock periods after the Low state of the
0
1
RES pin is sampled. Both pins are initialized to the output state.
471

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