HD6435348R Hitachi Semiconductor, HD6435348R Datasheet - Page 305

• Manufacturer Part Number: HD6435348R
• Description: Single-Chip Microcomputer
• Manufacturer: Hitachi Semiconductor

15.4 Operation
The A/D converter performs 10 successive approximations to obtain a result ranging from H'0000
(corresponding to AV
are significant.
The A/D converter module can be programmed to operate in single mode or scan mode as
explained below.
15.4.1 Single Mode (SCAN = 0)
The single mode is suitable for obtaining a single data value from a single channel. A/D
conversion starts when the ADST bit is set to 1. During the conversion process the ADST bit
remains set to 1. When conversion is completed, the ADST bit is automatically cleared to 0.
When the conversion is completed, the ADF bit is set to 1. If the interrupt enable bit (ADIE) is
also set to 1, an A/D conversion end interrupt (ADI) is requested, so that the converted data can be
processed by an interrupt-handling routine. Alternatively, the interrupt can be served by the data
transfer controller (DTC).
When an A/D interrupt is served by the DTC, the DTC automatically clears the ADF bit to 0.
When an A/D interrupt is served by the CPU, however, the ADF bit remains set until the CPU
reads the ADCSR, then writes a 0 in the ADF bit.
Before selecting the single mode, clock, and analog input channel, software should clear the
ADST bit to 0 to make sure the A/D converter is stopped. Changing the mode, clock, or channel
selection while A/D conversion is in progress can lead to conversion errors.
The following example explains the A/D conversion process in single mode when channel 1
(AN
1. Software clears the ADST bit to 0, then selects the single mode (SCAN = 0) and channel 1
2. The A/D converter samples the AN
(CH2 to CH0 = “001”), enables the A/D interrupt request (ADIE = 1), and sets the ADST bit to
1 to start A/D conversion. (Selection of mode, clock channel and setting the ADST bit can be
done at same time.)
Coding Example: (when using the slow clock, CKS = 0)
BCLR #5, @H'FEE8
MOV.B #H'61, @H'FEE8
the end of the conversion process the A/D converter transfers the result to register ADDRB,
sets the ADF bit is set to 1, clears the ADST bit to 0, and halts.
1
) is selected. Figure 15-3 shows the corresponding timing chart.
SS
) to H'FFC0 (corresponding to AV
1
input and converts the voltage level to a digital value. At
291
CC
). Only the first 10 bits of the result