HD6435348R Hitachi Semiconductor, HD6435348R Datasheet - Page 136

• Manufacturer Part Number: HD6435348R
• Description: Single-Chip Microcomputer
• Manufacturer: Hitachi Semiconductor

The data transfer count register is a 16-bit register that counts the number of bytes or words of
data remaining to be transferred. The initial count can be set from 1 to 65,536. A register value
of 0 designates an initial count of 65,536.
The data transfer count register is decremented automatically after each byte or word is transferred.
When its value reaches 0, indicating that the designated number of bytes or words have been
transferred, a CPU interrupt is generated with the vector of the interrupt that requested the data transfer.
6.2.5 Data Transfer Enable Registers A to F (DTEA to DTEF)
These six registers designate whether an interrupt starts the DTC. The bits in these registers are
assigned to interrupts as indicated in table 6-3. No bits are assigned to the NMI, FOVI, OVI, and
ERI interrupts, which cannot request data transfers.
Bit
Initial value
Read/Write
Table 6-3 Assignment of Data Transfer Enable Registers
Register Module
DTEA
DTEB
DTEC
DTED
DTEE
DTEF
Note: Bits marked “—” should always be cleared to 0.
If the bit for a certain interrupt is set to 1, that interrupt is regarded as a request for DTC service.
If the bit is cleared to 0, the interrupt is regarded as a CPU interrupt request.
Interrupt
Source or
IRQ
IRQ
16-Bit FRT1
16-Bit FRT3
SCI1
A/D converter
0
2
, IRQ
R/W
7
0
3
Bits 7 to 4
—
—
—
—
—
—
7
R/W
6
0
OCIB1 OCIA1 ICI1
OCIB3 OCIA3 ICI3
TXI1
—
—
—
6
R/W
5
0
IRQ
RXI1
—
—
5
3
117
R/W
IRQ
IRQ
ADI
4
0
—
4
0
2
Interrupt
Source or
Module
IRQ
IRQ
16-Bit FRT2
8-Bit Timer
SCI2
R/W
3
0
1
4
, IRQ
5
Bits 3 to 0
R/W
2
0
—
—
—
—
—
—
3
OCIB2 OCIA2 ICI2
TXI2
R/W
—
—
—
—
2
1
0
CMIB CMIA
IRQ
RXI2
—
—
1
R/W
5
0
0
IRQ
IRQ
—
—
0
1
4