HD6435348R Hitachi Semiconductor, HD6435348R Datasheet - Page 300

• Manufacturer Part Number: HD6435348R
• Description: Single-Chip Microcomputer
• Manufacturer: Hitachi Semiconductor

15.2 Register Descriptions
15.2.1 A/D Data Registers (ADDR)—H'FEE0 to H'FEE7
Bit
ADDRn H
Initial value
Read/Write
Bit
ADDRn H
Initial value
Read/Write
The four A/D data registers (ADDRA to ADDRD) are 16-bit read-only registers that store the
results of A/D conversion.
Each result consist of 10 bits. The first 8 bits are stored in the upper byte of the data register
corresponding to the selected channel. The last two bits are stored in the lower data register byte.
Each data register is assigned to two analog input channels as indicated in table 15-3.
The A/D data registers are always readable by the CPU. The upper byte can be read directly. The
lower byte is read via a temporary register. See section 15-3, “CPU Interface” for details.
The unused bits (bits 5 to 0) of the lower data register byte are always read as 0.
The A/D data registers are initialized to H'0000 at a reset and in the standby modes.
Table 15-3 Assignment of Data Registers to Analog Input Channels
Analog Input Channel
Group 0
AN
AN
AN
AN
0
1
2
3
Group 1
AN
AN
AN
AN
4
5
6
7
AD
AD
R
R
7
0
7
0
9
1
A/D Data Register
ADDRA
ADDRB
ADDRC
ADDRD
AD
AD
R
R
6
0
6
0
8
0
AD
—
R
R
5
0
5
0
7
286
AD
—
R
R
4
0
4
0
6
AD
—
R
R
3
0
3
0
5
AD
—
R
R
2
0
2
0
4
(n = A to D)
(n = A to D)
AD
—
R
R
1
0
1
0
3
AD
—
R
R
0
0
0
0
2